diff -ru u-boot-1.1.6.orig/common/cmd_flash.c u-boot-1.1.6/common/cmd_flash.c --- u-boot-1.1.6.orig/common/cmd_flash.c 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/common/cmd_flash.c 2007-01-16 14:44:09.000000000 +0100 @@ -690,7 +690,7 @@ ); U_BOOT_CMD( - erase, 3, 1, do_flerase, + erase, 3, 0, do_flerase, "erase - erase FLASH memory\n", "start end\n" " - erase FLASH from addr 'start' to addr 'end'\n" diff -ru u-boot-1.1.6.orig/common/cmd_net.c u-boot-1.1.6/common/cmd_net.c --- u-boot-1.1.6.orig/common/cmd_net.c 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/common/cmd_net.c 2007-01-16 14:44:09.000000000 +0100 @@ -151,12 +151,16 @@ #endif } +#ifndef CFG_DIRECT_FLASH_TFTP +extern flash_info_t flash_info[]; +#endif + static int netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) { char *s; int rcode = 0; - int size; + int size, i; /* pre-set load_addr */ if ((s = getenv("loadaddr")) != NULL) { @@ -187,6 +191,17 @@ return 1; } +#ifndef CFG_DIRECT_FLASH_TFTP + for (i=0; i= flash_info[i].start[0] && + load_addr < flash_info[i].start[0] + flash_info[i].size) { + printf("load address is in flash. Will not overwrite\n"); + return 1; + } + } +#endif + if ((size = NetLoop(proto)) < 0) return 1; diff -ru u-boot-1.1.6.orig/common/Makefile u-boot-1.1.6/common/Makefile --- u-boot-1.1.6.orig/common/Makefile 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/common/Makefile 2007-01-16 14:44:09.000000000 +0100 @@ -30,7 +30,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ cmd_ace.o cmd_autoscript.o \ cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \ - cmd_cache.o cmd_console.o \ + cmd_cache.o cmd_chggpio.o cmd_console.o \ cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \ cmd_eeprom.o cmd_elf.o cmd_ext2.o \ cmd_fat.o cmd_fdc.o cmd_fdos.o cmd_flash.o cmd_fpga.o \ @@ -38,7 +38,7 @@ cmd_load.o cmd_log.o \ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \ - cmd_pci.o cmd_pcmcia.o cmd_portio.o \ + cmd_pxagpio.o cmd_pci.o cmd_pcmcia.o cmd_portio.o \ cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ cmd_usb.o cmd_vfd.o \ command.o console.o devices.o dlmalloc.o docecc.o \ diff -ru u-boot-1.1.6.orig/cpu/pxa/pxafb.c u-boot-1.1.6/cpu/pxa/pxafb.c --- u-boot-1.1.6.orig/cpu/pxa/pxafb.c 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/cpu/pxa/pxafb.c 2007-01-16 14:44:09.000000000 +0100 @@ -147,6 +147,38 @@ #endif /* CONFIG_HITACHI_SX14 */ /*----------------------------------------------------------------------*/ +#ifdef CONFIG_SHARP_LQ084V1DG21 + +# define LCD_BPP LCD_COLOR8 +# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ + +/* you have to set lccr0 and lccr3 (including pcd) */ +# define REG_LCCR0 0x003008F9 +# define REG_LCCR3 0x03700001 + +vidinfo_t panel_info = { + vl_col: 640, + vl_row: 480, + vl_width: 171, + vl_height: 130, + vl_clkp: CFG_LOW, + vl_oep: CFG_HIGH, + vl_hsp: CFG_LOW, + vl_vsp: CFG_LOW, + vl_dp: CFG_HIGH, /* not used by PXA */ + vl_bpix: LCD_BPP, + vl_lbw: 1, + vl_splt: 0, + vl_clor: 1, + vl_tft: 1, + vl_hpw: 20, + vl_blw: 103, + vl_elw: 47, + vl_vpw: 6, + vl_bfw: 28, + vl_efw: 5, +}; +#endif /* CONFIG_SHARP_LQ084V1DG21 */ #if LCD_BPP == LCD_COLOR8 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); diff -ru u-boot-1.1.6.orig/cpu/pxa/serial.c u-boot-1.1.6/cpu/pxa/serial.c --- u-boot-1.1.6.orig/cpu/pxa/serial.c 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/cpu/pxa/serial.c 2007-01-16 14:44:09.000000000 +0100 @@ -61,7 +61,7 @@ #endif /* CONFIG_CPU_MONAHANS */ FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + FFFCR = FCR_TRFIFOE; /* Fifos enabled */ /* set baud rate */ FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; @@ -79,7 +79,7 @@ #endif /* CONFIG_CPU_MONAHANS */ BTIER = 0; - BTFCR = 0; + BTFCR = FCR_TRFIFOE; /* Fifos enabled */ /* set baud rate */ BTLCR = LCR_DLAB; diff -ru u-boot-1.1.6.orig/include/asm-arm/arch-pxa/pxa-regs.h u-boot-1.1.6/include/asm-arm/arch-pxa/pxa-regs.h --- u-boot-1.1.6.orig/include/asm-arm/arch-pxa/pxa-regs.h 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/include/asm-arm/arch-pxa/pxa-regs.h 2007-01-16 14:44:09.000000000 +0100 @@ -1269,15 +1269,15 @@ #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3) -#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3) -#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3) -#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3) -#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3) -#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3) -#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3) -#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \ - ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U)) +#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) +#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) +#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) +#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) +#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) +#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) +#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) +#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ + ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) #else #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) diff -ru u-boot-1.1.6.orig/include/asm-arm/global_data.h u-boot-1.1.6/include/asm-arm/global_data.h --- u-boot-1.1.6.orig/include/asm-arm/global_data.h 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/include/asm-arm/global_data.h 2007-01-16 14:44:09.000000000 +0100 @@ -61,6 +61,6 @@ #define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ #define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") +#define DECLARE_GLOBAL_DATA_PTR register gd_t *volatile gd asm ("r8") #endif /* __ASM_GBL_DATA_H */ diff -ru u-boot-1.1.6.orig/include/asm-arm/mach-types.h u-boot-1.1.6/include/asm-arm/mach-types.h --- u-boot-1.1.6.orig/include/asm-arm/mach-types.h 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/include/asm-arm/mach-types.h 2007-01-16 14:48:32.000000000 +0100 @@ -424,7 +424,7 @@ #define MACH_TYPE_MPORT3S 411 #define MACH_TYPE_RA_ALPHA 412 #define MACH_TYPE_XCEP 413 -#define MACH_TYPE_ARCOM_MERCURY 414 +#define MACH_TYPE_ARCOM_VULCAN 414 #define MACH_TYPE_STARGATE 415 #define MACH_TYPE_ARMADILLOJ 416 #define MACH_TYPE_ELROY_JACK 417 @@ -457,7 +457,7 @@ #define MACH_TYPE_XM250 444 #define MACH_TYPE_T6TC1XB 445 #define MACH_TYPE_ESS710 446 -#define MACH_TYPE_MX3ADS 447 +#define MACH_TYPE_MX31ADS 447 #define MACH_TYPE_HIMALAYA 448 #define MACH_TYPE_BOLFENK 449 #define MACH_TYPE_AT91RM9200KR 450 @@ -736,6 +736,236 @@ #define MACH_TYPE_LN2410SBC 725 #define MACH_TYPE_CB3RUFC 726 #define MACH_TYPE_MP2USB 727 +#define MACH_TYPE_NTNP425C 728 +#define MACH_TYPE_COLIBRI 729 +#define MACH_TYPE_PCM7220 730 +#define MACH_TYPE_GATEWAY7001 731 +#define MACH_TYPE_PCM027 732 +#define MACH_TYPE_CMPXA 733 +#define MACH_TYPE_ANUBIS 734 +#define MACH_TYPE_ITE8152 735 +#define MACH_TYPE_LPC3XXX 736 +#define MACH_TYPE_PUPPETEER 737 +#define MACH_TYPE_MACH_VADATECH 738 +#define MACH_TYPE_E570 739 +#define MACH_TYPE_X50 740 +#define MACH_TYPE_RECON 741 +#define MACH_TYPE_XBOARDGP8 742 +#define MACH_TYPE_FPIC2 743 +#define MACH_TYPE_AKITA 744 +#define MACH_TYPE_A81 745 +#define MACH_TYPE_SVM_SC25X 746 +#define MACH_TYPE_VADATECH020 747 +#define MACH_TYPE_TLI 748 +#define MACH_TYPE_EDB9315LC 749 +#define MACH_TYPE_PASSEC 750 +#define MACH_TYPE_DS_TIGER 751 +#define MACH_TYPE_E310 752 +#define MACH_TYPE_E330 753 +#define MACH_TYPE_RT3000 754 +#define MACH_TYPE_NOKIA770 755 +#define MACH_TYPE_PNX0106 756 +#define MACH_TYPE_HX21XX 757 +#define MACH_TYPE_FARADAY 758 +#define MACH_TYPE_SBC9312 759 +#define MACH_TYPE_BATMAN 760 +#define MACH_TYPE_JPD201 761 +#define MACH_TYPE_MIPSA 762 +#define MACH_TYPE_KACOM 763 +#define MACH_TYPE_SWARCOCPU 764 +#define MACH_TYPE_SWARCODSL 765 +#define MACH_TYPE_BLUEANGEL 766 +#define MACH_TYPE_HAIRYGRAMA 767 +#define MACH_TYPE_BANFF 768 +#define MACH_TYPE_CARMEVA 769 +#define MACH_TYPE_SAM255 770 +#define MACH_TYPE_PPM10 771 +#define MACH_TYPE_EDB9315A 772 +#define MACH_TYPE_SUNSET 773 +#define MACH_TYPE_STARGATE2 774 +#define MACH_TYPE_INTELMOTE2 775 +#define MACH_TYPE_TRIZEPS4 776 +#define MACH_TYPE_MAINSTONE2 777 +#define MACH_TYPE_EZ_IXP42X 778 +#define MACH_TYPE_TAPWAVE_ZODIAC 779 +#define MACH_TYPE_UNIVERSALMETER 780 +#define MACH_TYPE_HICOARM9 781 +#define MACH_TYPE_PNX4008 782 +#define MACH_TYPE_KWS6000 783 +#define MACH_TYPE_PORTUX920T 784 +#define MACH_TYPE_EZ_X5 785 +#define MACH_TYPE_OMAP_RUDOLPH 786 +#define MACH_TYPE_CPUAT91 787 +#define MACH_TYPE_REA9200 788 +#define MACH_TYPE_ACTS_PUNE_SA1110 789 +#define MACH_TYPE_IXP425 790 +#define MACH_TYPE_ARGONPLUSODYSSEY 791 +#define MACH_TYPE_PERCH 792 +#define MACH_TYPE_EIS05R1 793 +#define MACH_TYPE_PEPPERPAD 794 +#define MACH_TYPE_SB3010 795 +#define MACH_TYPE_RM9200 796 +#define MACH_TYPE_DMA03 797 +#define MACH_TYPE_ROAD_S101 798 +#define MACH_TYPE_IQ_NEXTGEN_A 799 +#define MACH_TYPE_IQ_NEXTGEN_B 800 +#define MACH_TYPE_IQ_NEXTGEN_C 801 +#define MACH_TYPE_IQ_NEXTGEN_D 802 +#define MACH_TYPE_IQ_NEXTGEN_E 803 +#define MACH_TYPE_MALLOW_AT91 804 +#define MACH_TYPE_CYBERTRACKER_I 805 +#define MACH_TYPE_GESBC931X 806 +#define MACH_TYPE_CENTIPAD 807 +#define MACH_TYPE_ARMSOC 808 +#define MACH_TYPE_SE4200 809 +#define MACH_TYPE_EMS197A 810 +#define MACH_TYPE_MICRO9 811 +#define MACH_TYPE_MICRO9L 812 +#define MACH_TYPE_UC5471DSP 813 +#define MACH_TYPE_SJ5471ENG 814 +#define MACH_TYPE_CMPXA26X 815 +#define MACH_TYPE_NC 816 +#define MACH_TYPE_OMAP_PALMTE 817 +#define MACH_TYPE_AJAX52X 818 +#define MACH_TYPE_SIRIUSTAR 819 +#define MACH_TYPE_IODATA_HDLG 820 +#define MACH_TYPE_AT91RM9200UTL 821 +#define MACH_TYPE_BIOSAFE 822 +#define MACH_TYPE_MP1000 823 +#define MACH_TYPE_PARSY 824 +#define MACH_TYPE_CCXP 825 +#define MACH_TYPE_OMAP_GSAMPLE 826 +#define MACH_TYPE_REALVIEW_EB 827 +#define MACH_TYPE_SAMOA 828 +#define MACH_TYPE_T3XSCALE 829 +#define MACH_TYPE_I878 830 +#define MACH_TYPE_BORZOI 831 +#define MACH_TYPE_GECKO 832 +#define MACH_TYPE_DS101 833 +#define MACH_TYPE_OMAP_PALMTT2 834 +#define MACH_TYPE_XSCALE_PALMLD 835 +#define MACH_TYPE_CC9C 836 +#define MACH_TYPE_SBC1670 837 +#define MACH_TYPE_IXDP28X5 838 +#define MACH_TYPE_OMAP_PALMTT 839 +#define MACH_TYPE_ML696K 840 +#define MACH_TYPE_ARCOM_ZEUS 841 +#define MACH_TYPE_OSIRIS 842 +#define MACH_TYPE_MAESTRO 843 +#define MACH_TYPE_TUNGE2 844 +#define MACH_TYPE_IXBBM 845 +#define MACH_TYPE_MX27 846 +#define MACH_TYPE_AX8004 847 +#define MACH_TYPE_AT91SAM9261EK 848 +#define MACH_TYPE_LOFT 849 +#define MACH_TYPE_MAGPIE 850 +#define MACH_TYPE_MX21 851 +#define MACH_TYPE_MB87M3400 852 +#define MACH_TYPE_MGUARD_DELTA 853 +#define MACH_TYPE_DAVINCI_DVDP 854 +#define MACH_TYPE_HTCUNIVERSAL 855 +#define MACH_TYPE_TPAD 856 +#define MACH_TYPE_ROVERP3 857 +#define MACH_TYPE_JORNADA928 858 +#define MACH_TYPE_MV88FXX81 859 +#define MACH_TYPE_STMP36XX 860 +#define MACH_TYPE_SXNI79524 861 +#define MACH_TYPE_AMS_DELTA 862 +#define MACH_TYPE_URANIUM 863 +#define MACH_TYPE_UCON 864 +#define MACH_TYPE_NAS100D 865 +#define MACH_TYPE_L083_1000 866 +#define MACH_TYPE_EZX 867 +#define MACH_TYPE_PNX5220 868 +#define MACH_TYPE_BUTTE 869 +#define MACH_TYPE_SRM2 870 +#define MACH_TYPE_DSBR 871 +#define MACH_TYPE_CRYSTALBALL 872 +#define MACH_TYPE_TINYPXA27X 873 +#define MACH_TYPE_HERBIE 874 +#define MACH_TYPE_MAGICIAN 875 +#define MACH_TYPE_CM4002 876 +#define MACH_TYPE_B4 877 +#define MACH_TYPE_MAUI 878 +#define MACH_TYPE_CYBERTRACKER_G 879 +#define MACH_TYPE_NXDKN 880 +#define MACH_TYPE_MIO8390 881 +#define MACH_TYPE_OMI_BOARD 882 +#define MACH_TYPE_MX21CIV 883 +#define MACH_TYPE_MAHI_CDAC 884 +#define MACH_TYPE_XSCALE_PALMTX 885 +#define MACH_TYPE_S3C2413 887 +#define MACH_TYPE_SAMSYS_EP0 888 +#define MACH_TYPE_WG302V1 889 +#define MACH_TYPE_WG302V2 890 +#define MACH_TYPE_EB42X 891 +#define MACH_TYPE_IQ331ES 892 +#define MACH_TYPE_COSYDSP 893 +#define MACH_TYPE_UPLAT7D 894 +#define MACH_TYPE_PTDAVINCI 895 +#define MACH_TYPE_MBUS 896 +#define MACH_TYPE_NADIA2VB 897 +#define MACH_TYPE_R1000 898 +#define MACH_TYPE_HW90250 899 +#define MACH_TYPE_OMAP_2430SDP 900 +#define MACH_TYPE_DAVINCI_EVM 901 +#define MACH_TYPE_OMAP_TORNADO 902 +#define MACH_TYPE_OLOCREEK 903 +#define MACH_TYPE_PALMZ72 904 +#define MACH_TYPE_NXDB500 905 +#define MACH_TYPE_APF9328 906 +#define MACH_TYPE_OMAP_WIPOQ 907 +#define MACH_TYPE_OMAP_TWIP 908 +#define MACH_TYPE_XSCALE_PALMTREO650 909 +#define MACH_TYPE_ACUMEN 910 +#define MACH_TYPE_XP100 911 +#define MACH_TYPE_FS2410 912 +#define MACH_TYPE_PXA270_CERF 913 +#define MACH_TYPE_SQ2FTLPALM 914 +#define MACH_TYPE_BSEMSERVER 915 +#define MACH_TYPE_NETCLIENT 916 +#define MACH_TYPE_XSCALE_PALMTT5 917 +#define MACH_TYPE_OMAP_PALMTC 918 +#define MACH_TYPE_OMAP_APOLLON 919 +#define MACH_TYPE_ARGONLVEVB 920 +#define MACH_TYPE_REA_2D 921 +#define MACH_TYPE_TI3E524 922 +#define MACH_TYPE_ATEB9200 923 +#define MACH_TYPE_AUCKLAND 924 +#define MACH_TYPE_AK3320M 925 +#define MACH_TYPE_DURAMAX 926 +#define MACH_TYPE_N35 927 +#define MACH_TYPE_PRONGHORN 928 +#define MACH_TYPE_FUNDY 929 +#define MACH_TYPE_LOGICPD_PXA270 930 +#define MACH_TYPE_CPU777 931 +#define MACH_TYPE_SIMICON9201 932 +#define MACH_TYPE_LEAP2_HPM 933 +#define MACH_TYPE_CM922TXA10 934 +#define MACH_TYPE_PXA 935 +#define MACH_TYPE_SANDGATE2 936 +#define MACH_TYPE_SANDGATE2G 937 +#define MACH_TYPE_SANDGATE2P 938 +#define MACH_TYPE_FRED_JACK 939 +#define MACH_TYPE_TTG_COLOR1 940 +#define MACH_TYPE_NXEB500HMI 941 +#define MACH_TYPE_NETDCU8 942 +#define MACH_TYPE_ML675050_CPU_BOA 943 +#define MACH_TYPE_NG_FVX538 944 +#define MACH_TYPE_NG_FVS338 945 +#define MACH_TYPE_PNX4103 946 +#define MACH_TYPE_HESDB 947 +#define MACH_TYPE_XSILO 948 +#define MACH_TYPE_ESPRESSO 949 +#define MACH_TYPE_EMLC 950 +#define MACH_TYPE_SISTERON 951 +#define MACH_TYPE_RX1950 952 +#define MACH_TYPE_TSC_VENUS 953 +#define MACH_TYPE_DS101J 954 +#define MACH_TYPE_MXC30030ADS 955 +#define MACH_TYPE_FUJITSU_WIMAXSOC 956 +#define MACH_TYPE_DUALPCMODEM 957 +#define MACH_TYPE_GESBC9312 958 #define MACH_TYPE_PDNB3 1002 #ifdef CONFIG_ARCH_EBSA110 @@ -3541,9 +3771,9 @@ # else # define machine_arch_type MACH_TYPE_RAMSES # endif -# define machine_is_ramses() (machine_arch_type == MACH_TYPE_RAMSES) +# define machine_is_mnci() (machine_arch_type == MACH_TYPE_RAMSES) #else -# define machine_is_ramses() (0) +# define machine_is_mnci() (0) #endif #ifdef CONFIG_ARCH_S28X @@ -4501,9 +4731,9 @@ # else # define machine_arch_type MACH_TYPE_M825XX # endif -# define machine_is_m825xx() (machine_arch_type == MACH_TYPE_M825XX) +# define machine_is_comcerto() (machine_arch_type == MACH_TYPE_M825XX) #else -# define machine_is_m825xx() (0) +# define machine_is_comcerto() (0) #endif #ifdef CONFIG_SA1100_M7100 @@ -5658,16 +5888,16 @@ # define machine_is_xcep() (0) #endif -#ifdef CONFIG_MACH_ARCOM_MERCURY +#ifdef CONFIG_MACH_ARCOM_VULCAN # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_ARCOM_MERCURY +# define machine_arch_type MACH_TYPE_ARCOM_VULCAN # endif -# define machine_is_arcom_mercury() (machine_arch_type == MACH_TYPE_ARCOM_MERCURY) +# define machine_is_arcom_vulcan() (machine_arch_type == MACH_TYPE_ARCOM_VULCAN) #else -# define machine_is_arcom_mercury() (0) +# define machine_is_arcom_vulcan() (0) #endif #ifdef CONFIG_MACH_STARGATE @@ -6054,16 +6284,16 @@ # define machine_is_ess710() (0) #endif -#ifdef CONFIG_MACH_MX3ADS +#ifdef CONFIG_MACH_MX31ADS # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_MX3ADS +# define machine_arch_type MACH_TYPE_MX31ADS # endif -# define machine_is_mx3ads() (machine_arch_type == MACH_TYPE_MX3ADS) +# define machine_is_mx31ads() (machine_arch_type == MACH_TYPE_MX31ADS) #else -# define machine_is_mx3ads() (0) +# define machine_is_mx31ads() (0) #endif #ifdef CONFIG_MACH_HIMALAYA @@ -9402,6 +9632,2766 @@ # define machine_is_mp2usb() (0) #endif +#ifdef CONFIG_MACH_NTNP425C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NTNP425C +# endif +# define machine_is_ntnp425c() (machine_arch_type == MACH_TYPE_NTNP425C) +#else +# define machine_is_ntnp425c() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI +# endif +# define machine_is_colibri() (machine_arch_type == MACH_TYPE_COLIBRI) +#else +# define machine_is_colibri() (0) +#endif + +#ifdef CONFIG_MACH_PCM7220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM7220 +# endif +# define machine_is_pcm7220() (machine_arch_type == MACH_TYPE_PCM7220) +#else +# define machine_is_pcm7220() (0) +#endif + +#ifdef CONFIG_MACH_GATEWAY7001 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GATEWAY7001 +# endif +# define machine_is_gateway7001() (machine_arch_type == MACH_TYPE_GATEWAY7001) +#else +# define machine_is_gateway7001() (0) +#endif + +#ifdef CONFIG_MACH_PCM027 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM027 +# endif +# define machine_is_pcm027() (machine_arch_type == MACH_TYPE_PCM027) +#else +# define machine_is_pcm027() (0) +#endif + +#ifdef CONFIG_MACH_CMPXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPXA +# endif +# define machine_is_cmpxa() (machine_arch_type == MACH_TYPE_CMPXA) +#else +# define machine_is_cmpxa() (0) +#endif + +#ifdef CONFIG_MACH_ANUBIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANUBIS +# endif +# define machine_is_anubis() (machine_arch_type == MACH_TYPE_ANUBIS) +#else +# define machine_is_anubis() (0) +#endif + +#ifdef CONFIG_MACH_ITE8152 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ITE8152 +# endif +# define machine_is_ite8152() (machine_arch_type == MACH_TYPE_ITE8152) +#else +# define machine_is_ite8152() (0) +#endif + +#ifdef CONFIG_MACH_LPC3XXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC3XXX +# endif +# define machine_is_lpc3xxx() (machine_arch_type == MACH_TYPE_LPC3XXX) +#else +# define machine_is_lpc3xxx() (0) +#endif + +#ifdef CONFIG_MACH_PUPPETEER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PUPPETEER +# endif +# define machine_is_puppeteer() (machine_arch_type == MACH_TYPE_PUPPETEER) +#else +# define machine_is_puppeteer() (0) +#endif + +#ifdef CONFIG_MACH_MACH_VADATECH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MACH_VADATECH +# endif +# define machine_is_vt001() (machine_arch_type == MACH_TYPE_MACH_VADATECH) +#else +# define machine_is_vt001() (0) +#endif + +#ifdef CONFIG_MACH_E570 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E570 +# endif +# define machine_is_e570() (machine_arch_type == MACH_TYPE_E570) +#else +# define machine_is_e570() (0) +#endif + +#ifdef CONFIG_MACH_X50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_X50 +# endif +# define machine_is_x50() (machine_arch_type == MACH_TYPE_X50) +#else +# define machine_is_x50() (0) +#endif + +#ifdef CONFIG_MACH_RECON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RECON +# endif +# define machine_is_recon() (machine_arch_type == MACH_TYPE_RECON) +#else +# define machine_is_recon() (0) +#endif + +#ifdef CONFIG_MACH_XBOARDGP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XBOARDGP8 +# endif +# define machine_is_xboardgp8() (machine_arch_type == MACH_TYPE_XBOARDGP8) +#else +# define machine_is_xboardgp8() (0) +#endif + +#ifdef CONFIG_MACH_FPIC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FPIC2 +# endif +# define machine_is_fpic2() (machine_arch_type == MACH_TYPE_FPIC2) +#else +# define machine_is_fpic2() (0) +#endif + +#ifdef CONFIG_MACH_AKITA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AKITA +# endif +# define machine_is_akita() (machine_arch_type == MACH_TYPE_AKITA) +#else +# define machine_is_akita() (0) +#endif + +#ifdef CONFIG_MACH_A81 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A81 +# endif +# define machine_is_a81() (machine_arch_type == MACH_TYPE_A81) +#else +# define machine_is_a81() (0) +#endif + +#ifdef CONFIG_MACH_SVM_SC25X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SVM_SC25X +# endif +# define machine_is_svm_sc25x() (machine_arch_type == MACH_TYPE_SVM_SC25X) +#else +# define machine_is_svm_sc25x() (0) +#endif + +#ifdef CONFIG_MACH_VADATECH020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VADATECH020 +# endif +# define machine_is_vt020() (machine_arch_type == MACH_TYPE_VADATECH020) +#else +# define machine_is_vt020() (0) +#endif + +#ifdef CONFIG_MACH_TLI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TLI +# endif +# define machine_is_tli() (machine_arch_type == MACH_TYPE_TLI) +#else +# define machine_is_tli() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315LC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315LC +# endif +# define machine_is_edb9315lc() (machine_arch_type == MACH_TYPE_EDB9315LC) +#else +# define machine_is_edb9315lc() (0) +#endif + +#ifdef CONFIG_MACH_PASSEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSEC +# endif +# define machine_is_passec() (machine_arch_type == MACH_TYPE_PASSEC) +#else +# define machine_is_passec() (0) +#endif + +#ifdef CONFIG_MACH_DS_TIGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS_TIGER +# endif +# define machine_is_ds_tiger() (machine_arch_type == MACH_TYPE_DS_TIGER) +#else +# define machine_is_ds_tiger() (0) +#endif + +#ifdef CONFIG_MACH_E310 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E310 +# endif +# define machine_is_e310() (machine_arch_type == MACH_TYPE_E310) +#else +# define machine_is_e310() (0) +#endif + +#ifdef CONFIG_MACH_E330 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E330 +# endif +# define machine_is_e330() (machine_arch_type == MACH_TYPE_E330) +#else +# define machine_is_e330() (0) +#endif + +#ifdef CONFIG_MACH_RT3000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RT3000 +# endif +# define machine_is_rt3000() (machine_arch_type == MACH_TYPE_RT3000) +#else +# define machine_is_rt3000() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA770 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA770 +# endif +# define machine_is_nokia770() (machine_arch_type == MACH_TYPE_NOKIA770) +#else +# define machine_is_nokia770() (0) +#endif + +#ifdef CONFIG_MACH_PNX0106 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX0106 +# endif +# define machine_is_pnx0106() (machine_arch_type == MACH_TYPE_PNX0106) +#else +# define machine_is_pnx0106() (0) +#endif + +#ifdef CONFIG_MACH_HX21XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HX21XX +# endif +# define machine_is_hx21xx() (machine_arch_type == MACH_TYPE_HX21XX) +#else +# define machine_is_hx21xx() (0) +#endif + +#ifdef CONFIG_MACH_FARADAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FARADAY +# endif +# define machine_is_faraday() (machine_arch_type == MACH_TYPE_FARADAY) +#else +# define machine_is_faraday() (0) +#endif + +#ifdef CONFIG_MACH_SBC9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC9312 +# endif +# define machine_is_sbc9312() (machine_arch_type == MACH_TYPE_SBC9312) +#else +# define machine_is_sbc9312() (0) +#endif + +#ifdef CONFIG_MACH_BATMAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BATMAN +# endif +# define machine_is_batman() (machine_arch_type == MACH_TYPE_BATMAN) +#else +# define machine_is_batman() (0) +#endif + +#ifdef CONFIG_MACH_JPD201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JPD201 +# endif +# define machine_is_jpd201() (machine_arch_type == MACH_TYPE_JPD201) +#else +# define machine_is_jpd201() (0) +#endif + +#ifdef CONFIG_MACH_MIPSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIPSA +# endif +# define machine_is_mipsa() (machine_arch_type == MACH_TYPE_MIPSA) +#else +# define machine_is_mipsa() (0) +#endif + +#ifdef CONFIG_MACH_KACOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KACOM +# endif +# define machine_is_kacom() (machine_arch_type == MACH_TYPE_KACOM) +#else +# define machine_is_kacom() (0) +#endif + +#ifdef CONFIG_MACH_SWARCOCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCOCPU +# endif +# define machine_is_swarcocpu() (machine_arch_type == MACH_TYPE_SWARCOCPU) +#else +# define machine_is_swarcocpu() (0) +#endif + +#ifdef CONFIG_MACH_SWARCODSL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCODSL +# endif +# define machine_is_swarcodsl() (machine_arch_type == MACH_TYPE_SWARCODSL) +#else +# define machine_is_swarcodsl() (0) +#endif + +#ifdef CONFIG_MACH_BLUEANGEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLUEANGEL +# endif +# define machine_is_blueangel() (machine_arch_type == MACH_TYPE_BLUEANGEL) +#else +# define machine_is_blueangel() (0) +#endif + +#ifdef CONFIG_MACH_HAIRYGRAMA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HAIRYGRAMA +# endif +# define machine_is_hairygrama() (machine_arch_type == MACH_TYPE_HAIRYGRAMA) +#else +# define machine_is_hairygrama() (0) +#endif + +#ifdef CONFIG_MACH_BANFF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BANFF +# endif +# define machine_is_banff() (machine_arch_type == MACH_TYPE_BANFF) +#else +# define machine_is_banff() (0) +#endif + +#ifdef CONFIG_MACH_CARMEVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CARMEVA +# endif +# define machine_is_carmeva() (machine_arch_type == MACH_TYPE_CARMEVA) +#else +# define machine_is_carmeva() (0) +#endif + +#ifdef CONFIG_MACH_SAM255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAM255 +# endif +# define machine_is_sam255() (machine_arch_type == MACH_TYPE_SAM255) +#else +# define machine_is_sam255() (0) +#endif + +#ifdef CONFIG_MACH_PPM10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PPM10 +# endif +# define machine_is_ppm10() (machine_arch_type == MACH_TYPE_PPM10) +#else +# define machine_is_ppm10() (0) +#endif + +#ifdef CONFIG_MACH_EDB9315A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDB9315A +# endif +# define machine_is_edb9315a() (machine_arch_type == MACH_TYPE_EDB9315A) +#else +# define machine_is_edb9315a() (0) +#endif + +#ifdef CONFIG_MACH_SUNSET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUNSET +# endif +# define machine_is_sunset() (machine_arch_type == MACH_TYPE_SUNSET) +#else +# define machine_is_sunset() (0) +#endif + +#ifdef CONFIG_MACH_STARGATE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STARGATE2 +# endif +# define machine_is_stargate2() (machine_arch_type == MACH_TYPE_STARGATE2) +#else +# define machine_is_stargate2() (0) +#endif + +#ifdef CONFIG_MACH_INTELMOTE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INTELMOTE2 +# endif +# define machine_is_intelmote2() (machine_arch_type == MACH_TYPE_INTELMOTE2) +#else +# define machine_is_intelmote2() (0) +#endif + +#ifdef CONFIG_MACH_TRIZEPS4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TRIZEPS4 +# endif +# define machine_is_trizeps4() (machine_arch_type == MACH_TYPE_TRIZEPS4) +#else +# define machine_is_trizeps4() (0) +#endif + +#ifdef CONFIG_MACH_MAINSTONE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAINSTONE2 +# endif +# define machine_is_mainstone2() (machine_arch_type == MACH_TYPE_MAINSTONE2) +#else +# define machine_is_mainstone2() (0) +#endif + +#ifdef CONFIG_MACH_EZ_IXP42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_IXP42X +# endif +# define machine_is_ez_ixp42x() (machine_arch_type == MACH_TYPE_EZ_IXP42X) +#else +# define machine_is_ez_ixp42x() (0) +#endif + +#ifdef CONFIG_MACH_TAPWAVE_ZODIAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAPWAVE_ZODIAC +# endif +# define machine_is_tapwave_zodiac() (machine_arch_type == MACH_TYPE_TAPWAVE_ZODIAC) +#else +# define machine_is_tapwave_zodiac() (0) +#endif + +#ifdef CONFIG_MACH_UNIVERSALMETER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIVERSALMETER +# endif +# define machine_is_universalmeter() (machine_arch_type == MACH_TYPE_UNIVERSALMETER) +#else +# define machine_is_universalmeter() (0) +#endif + +#ifdef CONFIG_MACH_HICOARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HICOARM9 +# endif +# define machine_is_hicoarm9() (machine_arch_type == MACH_TYPE_HICOARM9) +#else +# define machine_is_hicoarm9() (0) +#endif + +#ifdef CONFIG_MACH_PNX4008 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX4008 +# endif +# define machine_is_pnx4008() (machine_arch_type == MACH_TYPE_PNX4008) +#else +# define machine_is_pnx4008() (0) +#endif + +#ifdef CONFIG_MACH_KWS6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KWS6000 +# endif +# define machine_is_kws6000() (machine_arch_type == MACH_TYPE_KWS6000) +#else +# define machine_is_kws6000() (0) +#endif + +#ifdef CONFIG_MACH_PORTUX920T +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PORTUX920T +# endif +# define machine_is_portux920t() (machine_arch_type == MACH_TYPE_PORTUX920T) +#else +# define machine_is_portux920t() (0) +#endif + +#ifdef CONFIG_MACH_EZ_X5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZ_X5 +# endif +# define machine_is_ez_x5() (machine_arch_type == MACH_TYPE_EZ_X5) +#else +# define machine_is_ez_x5() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_RUDOLPH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_RUDOLPH +# endif +# define machine_is_omap_rudolph() (machine_arch_type == MACH_TYPE_OMAP_RUDOLPH) +#else +# define machine_is_omap_rudolph() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT91 +# endif +# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91) +#else +# define machine_is_cpuat91() (0) +#endif + +#ifdef CONFIG_MACH_REA9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA9200 +# endif +# define machine_is_rea9200() (machine_arch_type == MACH_TYPE_REA9200) +#else +# define machine_is_rea9200() (0) +#endif + +#ifdef CONFIG_MACH_ACTS_PUNE_SA1110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTS_PUNE_SA1110 +# endif +# define machine_is_acts_pune_sa1110() (machine_arch_type == MACH_TYPE_ACTS_PUNE_SA1110) +#else +# define machine_is_acts_pune_sa1110() (0) +#endif + +#ifdef CONFIG_MACH_IXP425 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXP425 +# endif +# define machine_is_ixp425() (machine_arch_type == MACH_TYPE_IXP425) +#else +# define machine_is_ixp425() (0) +#endif + +#ifdef CONFIG_MACH_ARGONPLUSODYSSEY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARGONPLUSODYSSEY +# endif +# define machine_is_argonplusodyssey() (machine_arch_type == MACH_TYPE_ARGONPLUSODYSSEY) +#else +# define machine_is_argonplusodyssey() (0) +#endif + +#ifdef CONFIG_MACH_PERCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PERCH +# endif +# define machine_is_perch() (machine_arch_type == MACH_TYPE_PERCH) +#else +# define machine_is_perch() (0) +#endif + +#ifdef CONFIG_MACH_EIS05R1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EIS05R1 +# endif +# define machine_is_eis05r1() (machine_arch_type == MACH_TYPE_EIS05R1) +#else +# define machine_is_eis05r1() (0) +#endif + +#ifdef CONFIG_MACH_PEPPERPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PEPPERPAD +# endif +# define machine_is_pepperpad() (machine_arch_type == MACH_TYPE_PEPPERPAD) +#else +# define machine_is_pepperpad() (0) +#endif + +#ifdef CONFIG_MACH_SB3010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SB3010 +# endif +# define machine_is_sb3010() (machine_arch_type == MACH_TYPE_SB3010) +#else +# define machine_is_sb3010() (0) +#endif + +#ifdef CONFIG_MACH_RM9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RM9200 +# endif +# define machine_is_rm9200() (machine_arch_type == MACH_TYPE_RM9200) +#else +# define machine_is_rm9200() (0) +#endif + +#ifdef CONFIG_MACH_DMA03 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DMA03 +# endif +# define machine_is_dma03() (machine_arch_type == MACH_TYPE_DMA03) +#else +# define machine_is_dma03() (0) +#endif + +#ifdef CONFIG_MACH_ROAD_S101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROAD_S101 +# endif +# define machine_is_road_s101() (machine_arch_type == MACH_TYPE_ROAD_S101) +#else +# define machine_is_road_s101() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_A +# endif +# define machine_is_iq_nextgen_a() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_A) +#else +# define machine_is_iq_nextgen_a() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_B +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_B +# endif +# define machine_is_iq_nextgen_b() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_B) +#else +# define machine_is_iq_nextgen_b() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_C +# endif +# define machine_is_iq_nextgen_c() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_C) +#else +# define machine_is_iq_nextgen_c() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_D +# endif +# define machine_is_iq_nextgen_d() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_D) +#else +# define machine_is_iq_nextgen_d() (0) +#endif + +#ifdef CONFIG_MACH_IQ_NEXTGEN_E +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ_NEXTGEN_E +# endif +# define machine_is_iq_nextgen_e() (machine_arch_type == MACH_TYPE_IQ_NEXTGEN_E) +#else +# define machine_is_iq_nextgen_e() (0) +#endif + +#ifdef CONFIG_MACH_MALLOW_AT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MALLOW_AT91 +# endif +# define machine_is_mallow_at91() (machine_arch_type == MACH_TYPE_MALLOW_AT91) +#else +# define machine_is_mallow_at91() (0) +#endif + +#ifdef CONFIG_MACH_CYBERTRACKER_I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBERTRACKER_I +# endif +# define machine_is_cybertracker_i() (machine_arch_type == MACH_TYPE_CYBERTRACKER_I) +#else +# define machine_is_cybertracker_i() (0) +#endif + +#ifdef CONFIG_MACH_GESBC931X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GESBC931X +# endif +# define machine_is_gesbc931x() (machine_arch_type == MACH_TYPE_GESBC931X) +#else +# define machine_is_gesbc931x() (0) +#endif + +#ifdef CONFIG_MACH_CENTIPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CENTIPAD +# endif +# define machine_is_centipad() (machine_arch_type == MACH_TYPE_CENTIPAD) +#else +# define machine_is_centipad() (0) +#endif + +#ifdef CONFIG_MACH_ARMSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMSOC +# endif +# define machine_is_armsoc() (machine_arch_type == MACH_TYPE_ARMSOC) +#else +# define machine_is_armsoc() (0) +#endif + +#ifdef CONFIG_MACH_SE4200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SE4200 +# endif +# define machine_is_se4200() (machine_arch_type == MACH_TYPE_SE4200) +#else +# define machine_is_se4200() (0) +#endif + +#ifdef CONFIG_MACH_EMS197A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS197A +# endif +# define machine_is_ems197a() (machine_arch_type == MACH_TYPE_EMS197A) +#else +# define machine_is_ems197a() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9 +# endif +# define machine_is_micro9() (machine_arch_type == MACH_TYPE_MICRO9) +#else +# define machine_is_micro9() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9L +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9L +# endif +# define machine_is_micro9l() (machine_arch_type == MACH_TYPE_MICRO9L) +#else +# define machine_is_micro9l() (0) +#endif + +#ifdef CONFIG_MACH_UC5471DSP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UC5471DSP +# endif +# define machine_is_uc5471dsp() (machine_arch_type == MACH_TYPE_UC5471DSP) +#else +# define machine_is_uc5471dsp() (0) +#endif + +#ifdef CONFIG_MACH_SJ5471ENG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SJ5471ENG +# endif +# define machine_is_sj5471eng() (machine_arch_type == MACH_TYPE_SJ5471ENG) +#else +# define machine_is_sj5471eng() (0) +#endif + +#ifdef CONFIG_MACH_CMPXA26X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CMPXA26X +# endif +# define machine_is_none() (machine_arch_type == MACH_TYPE_CMPXA26X) +#else +# define machine_is_none() (0) +#endif + +#ifdef CONFIG_MACH_NC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NC +# endif +# define machine_is_nc() (machine_arch_type == MACH_TYPE_NC) +#else +# define machine_is_nc() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTE +# endif +# define machine_is_omap_palmte() (machine_arch_type == MACH_TYPE_OMAP_PALMTE) +#else +# define machine_is_omap_palmte() (0) +#endif + +#ifdef CONFIG_MACH_AJAX52X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AJAX52X +# endif +# define machine_is_ajax52x() (machine_arch_type == MACH_TYPE_AJAX52X) +#else +# define machine_is_ajax52x() (0) +#endif + +#ifdef CONFIG_MACH_SIRIUSTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIRIUSTAR +# endif +# define machine_is_siriustar() (machine_arch_type == MACH_TYPE_SIRIUSTAR) +#else +# define machine_is_siriustar() (0) +#endif + +#ifdef CONFIG_MACH_IODATA_HDLG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IODATA_HDLG +# endif +# define machine_is_iodata_hdlg() (machine_arch_type == MACH_TYPE_IODATA_HDLG) +#else +# define machine_is_iodata_hdlg() (0) +#endif + +#ifdef CONFIG_MACH_AT91RM9200UTL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91RM9200UTL +# endif +# define machine_is_at91rm9200utl() (machine_arch_type == MACH_TYPE_AT91RM9200UTL) +#else +# define machine_is_at91rm9200utl() (0) +#endif + +#ifdef CONFIG_MACH_BIOSAFE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIOSAFE +# endif +# define machine_is_biosafe() (machine_arch_type == MACH_TYPE_BIOSAFE) +#else +# define machine_is_biosafe() (0) +#endif + +#ifdef CONFIG_MACH_MP1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MP1000 +# endif +# define machine_is_mp1000() (machine_arch_type == MACH_TYPE_MP1000) +#else +# define machine_is_mp1000() (0) +#endif + +#ifdef CONFIG_MACH_PARSY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARSY +# endif +# define machine_is_parsy() (machine_arch_type == MACH_TYPE_PARSY) +#else +# define machine_is_parsy() (0) +#endif + +#ifdef CONFIG_MACH_CCXP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCXP +# endif +# define machine_is_ccxp270() (machine_arch_type == MACH_TYPE_CCXP) +#else +# define machine_is_ccxp270() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_GSAMPLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_GSAMPLE +# endif +# define machine_is_omap_gsample() (machine_arch_type == MACH_TYPE_OMAP_GSAMPLE) +#else +# define machine_is_omap_gsample() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_EB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_EB +# endif +# define machine_is_realview_eb() (machine_arch_type == MACH_TYPE_REALVIEW_EB) +#else +# define machine_is_realview_eb() (0) +#endif + +#ifdef CONFIG_MACH_SAMOA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAMOA +# endif +# define machine_is_samoa() (machine_arch_type == MACH_TYPE_SAMOA) +#else +# define machine_is_samoa() (0) +#endif + +#ifdef CONFIG_MACH_T3XSCALE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_T3XSCALE +# endif +# define machine_is_t3xscale() (machine_arch_type == MACH_TYPE_T3XSCALE) +#else +# define machine_is_t3xscale() (0) +#endif + +#ifdef CONFIG_MACH_I878 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I878 +# endif +# define machine_is_i878() (machine_arch_type == MACH_TYPE_I878) +#else +# define machine_is_i878() (0) +#endif + +#ifdef CONFIG_MACH_BORZOI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BORZOI +# endif +# define machine_is_borzoi() (machine_arch_type == MACH_TYPE_BORZOI) +#else +# define machine_is_borzoi() (0) +#endif + +#ifdef CONFIG_MACH_GECKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GECKO +# endif +# define machine_is_gecko() (machine_arch_type == MACH_TYPE_GECKO) +#else +# define machine_is_gecko() (0) +#endif + +#ifdef CONFIG_MACH_DS101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS101 +# endif +# define machine_is_ds101() (machine_arch_type == MACH_TYPE_DS101) +#else +# define machine_is_ds101() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTT2 +# endif +# define machine_is_omap_palmtt2() (machine_arch_type == MACH_TYPE_OMAP_PALMTT2) +#else +# define machine_is_omap_palmtt2() (0) +#endif + +#ifdef CONFIG_MACH_XSCALE_PALMLD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSCALE_PALMLD +# endif +# define machine_is_xscale_palmld() (machine_arch_type == MACH_TYPE_XSCALE_PALMLD) +#else +# define machine_is_xscale_palmld() (0) +#endif + +#ifdef CONFIG_MACH_CC9C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9C +# endif +# define machine_is_cc9c() (machine_arch_type == MACH_TYPE_CC9C) +#else +# define machine_is_cc9c() (0) +#endif + +#ifdef CONFIG_MACH_SBC1670 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC1670 +# endif +# define machine_is_sbc1670() (machine_arch_type == MACH_TYPE_SBC1670) +#else +# define machine_is_sbc1670() (0) +#endif + +#ifdef CONFIG_MACH_IXDP28X5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXDP28X5 +# endif +# define machine_is_ixdp28x5() (machine_arch_type == MACH_TYPE_IXDP28X5) +#else +# define machine_is_ixdp28x5() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTT +# endif +# define machine_is_omap_palmtt() (machine_arch_type == MACH_TYPE_OMAP_PALMTT) +#else +# define machine_is_omap_palmtt() (0) +#endif + +#ifdef CONFIG_MACH_ML696K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML696K +# endif +# define machine_is_ml696k() (machine_arch_type == MACH_TYPE_ML696K) +#else +# define machine_is_ml696k() (0) +#endif + +#ifdef CONFIG_MACH_ARCOM_ZEUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCOM_ZEUS +# endif +# define machine_is_arcom_zeus() (machine_arch_type == MACH_TYPE_ARCOM_ZEUS) +#else +# define machine_is_arcom_zeus() (0) +#endif + +#ifdef CONFIG_MACH_OSIRIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OSIRIS +# endif +# define machine_is_osiris() (machine_arch_type == MACH_TYPE_OSIRIS) +#else +# define machine_is_osiris() (0) +#endif + +#ifdef CONFIG_MACH_MAESTRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAESTRO +# endif +# define machine_is_maestro() (machine_arch_type == MACH_TYPE_MAESTRO) +#else +# define machine_is_maestro() (0) +#endif + +#ifdef CONFIG_MACH_TUNGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TUNGE2 +# endif +# define machine_is_tunge2() (machine_arch_type == MACH_TYPE_TUNGE2) +#else +# define machine_is_tunge2() (0) +#endif + +#ifdef CONFIG_MACH_IXBBM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IXBBM +# endif +# define machine_is_ixbbm() (machine_arch_type == MACH_TYPE_IXBBM) +#else +# define machine_is_ixbbm() (0) +#endif + +#ifdef CONFIG_MACH_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX27 +# endif +# define machine_is_mx27ads() (machine_arch_type == MACH_TYPE_MX27) +#else +# define machine_is_mx27ads() (0) +#endif + +#ifdef CONFIG_MACH_AX8004 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AX8004 +# endif +# define machine_is_ax8004() (machine_arch_type == MACH_TYPE_AX8004) +#else +# define machine_is_ax8004() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9261EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9261EK +# endif +# define machine_is_at91sam9261ek() (machine_arch_type == MACH_TYPE_AT91SAM9261EK) +#else +# define machine_is_at91sam9261ek() (0) +#endif + +#ifdef CONFIG_MACH_LOFT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOFT +# endif +# define machine_is_loft() (machine_arch_type == MACH_TYPE_LOFT) +#else +# define machine_is_loft() (0) +#endif + +#ifdef CONFIG_MACH_MAGPIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGPIE +# endif +# define machine_is_magpie() (machine_arch_type == MACH_TYPE_MAGPIE) +#else +# define machine_is_magpie() (0) +#endif + +#ifdef CONFIG_MACH_MX21 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX21 +# endif +# define machine_is_mx21ads() (machine_arch_type == MACH_TYPE_MX21) +#else +# define machine_is_mx21ads() (0) +#endif + +#ifdef CONFIG_MACH_MB87M3400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MB87M3400 +# endif +# define machine_is_mb87m3400() (machine_arch_type == MACH_TYPE_MB87M3400) +#else +# define machine_is_mb87m3400() (0) +#endif + +#ifdef CONFIG_MACH_MGUARD_DELTA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MGUARD_DELTA +# endif +# define machine_is_mguard_delta() (machine_arch_type == MACH_TYPE_MGUARD_DELTA) +#else +# define machine_is_mguard_delta() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DVDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DVDP +# endif +# define machine_is_davinci_dvdp() (machine_arch_type == MACH_TYPE_DAVINCI_DVDP) +#else +# define machine_is_davinci_dvdp() (0) +#endif + +#ifdef CONFIG_MACH_HTCUNIVERSAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCUNIVERSAL +# endif +# define machine_is_htcuniversal() (machine_arch_type == MACH_TYPE_HTCUNIVERSAL) +#else +# define machine_is_htcuniversal() (0) +#endif + +#ifdef CONFIG_MACH_TPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TPAD +# endif +# define machine_is_tpad() (machine_arch_type == MACH_TYPE_TPAD) +#else +# define machine_is_tpad() (0) +#endif + +#ifdef CONFIG_MACH_ROVERP3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROVERP3 +# endif +# define machine_is_roverp3() (machine_arch_type == MACH_TYPE_ROVERP3) +#else +# define machine_is_roverp3() (0) +#endif + +#ifdef CONFIG_MACH_JORNADA928 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JORNADA928 +# endif +# define machine_is_jornada928() (machine_arch_type == MACH_TYPE_JORNADA928) +#else +# define machine_is_jornada928() (0) +#endif + +#ifdef CONFIG_MACH_MV88FXX81 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88FXX81 +# endif +# define machine_is_mv88fxx81() (machine_arch_type == MACH_TYPE_MV88FXX81) +#else +# define machine_is_mv88fxx81() (0) +#endif + +#ifdef CONFIG_MACH_STMP36XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STMP36XX +# endif +# define machine_is_stmp36xx() (machine_arch_type == MACH_TYPE_STMP36XX) +#else +# define machine_is_stmp36xx() (0) +#endif + +#ifdef CONFIG_MACH_SXNI79524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SXNI79524 +# endif +# define machine_is_sxni79524() (machine_arch_type == MACH_TYPE_SXNI79524) +#else +# define machine_is_sxni79524() (0) +#endif + +#ifdef CONFIG_MACH_AMS_DELTA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AMS_DELTA +# endif +# define machine_is_ams_delta() (machine_arch_type == MACH_TYPE_AMS_DELTA) +#else +# define machine_is_ams_delta() (0) +#endif + +#ifdef CONFIG_MACH_URANIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_URANIUM +# endif +# define machine_is_uranium() (machine_arch_type == MACH_TYPE_URANIUM) +#else +# define machine_is_uranium() (0) +#endif + +#ifdef CONFIG_MACH_UCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCON +# endif +# define machine_is_ucon() (machine_arch_type == MACH_TYPE_UCON) +#else +# define machine_is_ucon() (0) +#endif + +#ifdef CONFIG_MACH_NAS100D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS100D +# endif +# define machine_is_nas100d() (machine_arch_type == MACH_TYPE_NAS100D) +#else +# define machine_is_nas100d() (0) +#endif + +#ifdef CONFIG_MACH_L083_1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_L083_1000 +# endif +# define machine_is_l083() (machine_arch_type == MACH_TYPE_L083_1000) +#else +# define machine_is_l083() (0) +#endif + +#ifdef CONFIG_MACH_EZX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EZX +# endif +# define machine_is_ezx() (machine_arch_type == MACH_TYPE_EZX) +#else +# define machine_is_ezx() (0) +#endif + +#ifdef CONFIG_MACH_PNX5220 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX5220 +# endif +# define machine_is_pnx5220() (machine_arch_type == MACH_TYPE_PNX5220) +#else +# define machine_is_pnx5220() (0) +#endif + +#ifdef CONFIG_MACH_BUTTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUTTE +# endif +# define machine_is_butte() (machine_arch_type == MACH_TYPE_BUTTE) +#else +# define machine_is_butte() (0) +#endif + +#ifdef CONFIG_MACH_SRM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SRM2 +# endif +# define machine_is_srm2() (machine_arch_type == MACH_TYPE_SRM2) +#else +# define machine_is_srm2() (0) +#endif + +#ifdef CONFIG_MACH_DSBR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSBR +# endif +# define machine_is_dsbr() (machine_arch_type == MACH_TYPE_DSBR) +#else +# define machine_is_dsbr() (0) +#endif + +#ifdef CONFIG_MACH_CRYSTALBALL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CRYSTALBALL +# endif +# define machine_is_crystalball() (machine_arch_type == MACH_TYPE_CRYSTALBALL) +#else +# define machine_is_crystalball() (0) +#endif + +#ifdef CONFIG_MACH_TINYPXA27X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TINYPXA27X +# endif +# define machine_is_tinypxa27x() (machine_arch_type == MACH_TYPE_TINYPXA27X) +#else +# define machine_is_tinypxa27x() (0) +#endif + +#ifdef CONFIG_MACH_HERBIE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERBIE +# endif +# define machine_is_herbie() (machine_arch_type == MACH_TYPE_HERBIE) +#else +# define machine_is_herbie() (0) +#endif + +#ifdef CONFIG_MACH_MAGICIAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGICIAN +# endif +# define machine_is_magician() (machine_arch_type == MACH_TYPE_MAGICIAN) +#else +# define machine_is_magician() (0) +#endif + +#ifdef CONFIG_MACH_CM4002 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM4002 +# endif +# define machine_is_cm4002() (machine_arch_type == MACH_TYPE_CM4002) +#else +# define machine_is_cm4002() (0) +#endif + +#ifdef CONFIG_MACH_B4 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_B4 +# endif +# define machine_is_b4() (machine_arch_type == MACH_TYPE_B4) +#else +# define machine_is_b4() (0) +#endif + +#ifdef CONFIG_MACH_MAUI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAUI +# endif +# define machine_is_maui() (machine_arch_type == MACH_TYPE_MAUI) +#else +# define machine_is_maui() (0) +#endif + +#ifdef CONFIG_MACH_CYBERTRACKER_G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBERTRACKER_G +# endif +# define machine_is_cybertracker_g() (machine_arch_type == MACH_TYPE_CYBERTRACKER_G) +#else +# define machine_is_cybertracker_g() (0) +#endif + +#ifdef CONFIG_MACH_NXDKN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXDKN +# endif +# define machine_is_nxdkn() (machine_arch_type == MACH_TYPE_NXDKN) +#else +# define machine_is_nxdkn() (0) +#endif + +#ifdef CONFIG_MACH_MIO8390 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MIO8390 +# endif +# define machine_is_mio8390() (machine_arch_type == MACH_TYPE_MIO8390) +#else +# define machine_is_mio8390() (0) +#endif + +#ifdef CONFIG_MACH_OMI_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMI_BOARD +# endif +# define machine_is_omi_board() (machine_arch_type == MACH_TYPE_OMI_BOARD) +#else +# define machine_is_omi_board() (0) +#endif + +#ifdef CONFIG_MACH_MX21CIV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX21CIV +# endif +# define machine_is_mx21civ() (machine_arch_type == MACH_TYPE_MX21CIV) +#else +# define machine_is_mx21civ() (0) +#endif + +#ifdef CONFIG_MACH_MAHI_CDAC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHI_CDAC +# endif +# define machine_is_mahi_cdac() (machine_arch_type == MACH_TYPE_MAHI_CDAC) +#else +# define machine_is_mahi_cdac() (0) +#endif + +#ifdef CONFIG_MACH_XSCALE_PALMTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSCALE_PALMTX +# endif +# define machine_is_xscale_palmtx() (machine_arch_type == MACH_TYPE_XSCALE_PALMTX) +#else +# define machine_is_xscale_palmtx() (0) +#endif + +#ifdef CONFIG_MACH_S3C2413 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S3C2413 +# endif +# define machine_is_s3c2413() (machine_arch_type == MACH_TYPE_S3C2413) +#else +# define machine_is_s3c2413() (0) +#endif + +#ifdef CONFIG_MACH_SAMSYS_EP0 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAMSYS_EP0 +# endif +# define machine_is_samsys_ep0() (machine_arch_type == MACH_TYPE_SAMSYS_EP0) +#else +# define machine_is_samsys_ep0() (0) +#endif + +#ifdef CONFIG_MACH_WG302V1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WG302V1 +# endif +# define machine_is_wg302v1() (machine_arch_type == MACH_TYPE_WG302V1) +#else +# define machine_is_wg302v1() (0) +#endif + +#ifdef CONFIG_MACH_WG302V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WG302V2 +# endif +# define machine_is_wg302v2() (machine_arch_type == MACH_TYPE_WG302V2) +#else +# define machine_is_wg302v2() (0) +#endif + +#ifdef CONFIG_MACH_EB42X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB42X +# endif +# define machine_is_eb42x() (machine_arch_type == MACH_TYPE_EB42X) +#else +# define machine_is_eb42x() (0) +#endif + +#ifdef CONFIG_MACH_IQ331ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IQ331ES +# endif +# define machine_is_iq331es() (machine_arch_type == MACH_TYPE_IQ331ES) +#else +# define machine_is_iq331es() (0) +#endif + +#ifdef CONFIG_MACH_COSYDSP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COSYDSP +# endif +# define machine_is_cosydsp() (machine_arch_type == MACH_TYPE_COSYDSP) +#else +# define machine_is_cosydsp() (0) +#endif + +#ifdef CONFIG_MACH_UPLAT7D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UPLAT7D +# endif +# define machine_is_uplat7d_proto() (machine_arch_type == MACH_TYPE_UPLAT7D) +#else +# define machine_is_uplat7d_proto() (0) +#endif + +#ifdef CONFIG_MACH_PTDAVINCI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PTDAVINCI +# endif +# define machine_is_ptdavinci() (machine_arch_type == MACH_TYPE_PTDAVINCI) +#else +# define machine_is_ptdavinci() (0) +#endif + +#ifdef CONFIG_MACH_MBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MBUS +# endif +# define machine_is_mbus() (machine_arch_type == MACH_TYPE_MBUS) +#else +# define machine_is_mbus() (0) +#endif + +#ifdef CONFIG_MACH_NADIA2VB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NADIA2VB +# endif +# define machine_is_nadia2vb() (machine_arch_type == MACH_TYPE_NADIA2VB) +#else +# define machine_is_nadia2vb() (0) +#endif + +#ifdef CONFIG_MACH_R1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_R1000 +# endif +# define machine_is_r1000() (machine_arch_type == MACH_TYPE_R1000) +#else +# define machine_is_r1000() (0) +#endif + +#ifdef CONFIG_MACH_HW90250 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HW90250 +# endif +# define machine_is_hw90250() (machine_arch_type == MACH_TYPE_HW90250) +#else +# define machine_is_hw90250() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_2430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_2430SDP +# endif +# define machine_is_omap_2430sdp() (machine_arch_type == MACH_TYPE_OMAP_2430SDP) +#else +# define machine_is_omap_2430sdp() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_EVM +# endif +# define machine_is_davinci_evm() (machine_arch_type == MACH_TYPE_DAVINCI_EVM) +#else +# define machine_is_davinci_evm() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_TORNADO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_TORNADO +# endif +# define machine_is_omap_tornado() (machine_arch_type == MACH_TYPE_OMAP_TORNADO) +#else +# define machine_is_omap_tornado() (0) +#endif + +#ifdef CONFIG_MACH_OLOCREEK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OLOCREEK +# endif +# define machine_is_olocreek() (machine_arch_type == MACH_TYPE_OLOCREEK) +#else +# define machine_is_olocreek() (0) +#endif + +#ifdef CONFIG_MACH_PALMZ72 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PALMZ72 +# endif +# define machine_is_palmz72() (machine_arch_type == MACH_TYPE_PALMZ72) +#else +# define machine_is_palmz72() (0) +#endif + +#ifdef CONFIG_MACH_NXDB500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXDB500 +# endif +# define machine_is_nxdb500() (machine_arch_type == MACH_TYPE_NXDB500) +#else +# define machine_is_nxdb500() (0) +#endif + +#ifdef CONFIG_MACH_APF9328 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APF9328 +# endif +# define machine_is_apf9328() (machine_arch_type == MACH_TYPE_APF9328) +#else +# define machine_is_apf9328() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_WIPOQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_WIPOQ +# endif +# define machine_is_omap_wipoq() (machine_arch_type == MACH_TYPE_OMAP_WIPOQ) +#else +# define machine_is_omap_wipoq() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_TWIP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_TWIP +# endif +# define machine_is_omap_twip() (machine_arch_type == MACH_TYPE_OMAP_TWIP) +#else +# define machine_is_omap_twip() (0) +#endif + +#ifdef CONFIG_MACH_XSCALE_PALMTREO650 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSCALE_PALMTREO650 +# endif +# define machine_is_xscale_treo650() (machine_arch_type == MACH_TYPE_XSCALE_PALMTREO650) +#else +# define machine_is_xscale_treo650() (0) +#endif + +#ifdef CONFIG_MACH_ACUMEN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACUMEN +# endif +# define machine_is_acumen() (machine_arch_type == MACH_TYPE_ACUMEN) +#else +# define machine_is_acumen() (0) +#endif + +#ifdef CONFIG_MACH_XP100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XP100 +# endif +# define machine_is_xp100() (machine_arch_type == MACH_TYPE_XP100) +#else +# define machine_is_xp100() (0) +#endif + +#ifdef CONFIG_MACH_FS2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FS2410 +# endif +# define machine_is_fs2410() (machine_arch_type == MACH_TYPE_FS2410) +#else +# define machine_is_fs2410() (0) +#endif + +#ifdef CONFIG_MACH_PXA270_CERF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA270_CERF +# endif +# define machine_is_pxa270_cerf() (machine_arch_type == MACH_TYPE_PXA270_CERF) +#else +# define machine_is_pxa270_cerf() (0) +#endif + +#ifdef CONFIG_MACH_SQ2FTLPALM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SQ2FTLPALM +# endif +# define machine_is_sq2ftlpalm() (machine_arch_type == MACH_TYPE_SQ2FTLPALM) +#else +# define machine_is_sq2ftlpalm() (0) +#endif + +#ifdef CONFIG_MACH_BSEMSERVER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSEMSERVER +# endif +# define machine_is_bsemserver() (machine_arch_type == MACH_TYPE_BSEMSERVER) +#else +# define machine_is_bsemserver() (0) +#endif + +#ifdef CONFIG_MACH_NETCLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETCLIENT +# endif +# define machine_is_netclient() (machine_arch_type == MACH_TYPE_NETCLIENT) +#else +# define machine_is_netclient() (0) +#endif + +#ifdef CONFIG_MACH_XSCALE_PALMTT5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSCALE_PALMTT5 +# endif +# define machine_is_xscale_palmtt5() (machine_arch_type == MACH_TYPE_XSCALE_PALMTT5) +#else +# define machine_is_xscale_palmtt5() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_PALMTC +# endif +# define machine_is_xscale_palmtc() (machine_arch_type == MACH_TYPE_OMAP_PALMTC) +#else +# define machine_is_xscale_palmtc() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_APOLLON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_APOLLON +# endif +# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON) +#else +# define machine_is_omap_apollon() (0) +#endif + +#ifdef CONFIG_MACH_ARGONLVEVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARGONLVEVB +# endif +# define machine_is_argonlvevb() (machine_arch_type == MACH_TYPE_ARGONLVEVB) +#else +# define machine_is_argonlvevb() (0) +#endif + +#ifdef CONFIG_MACH_REA_2D +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REA_2D +# endif +# define machine_is_rea_2d() (machine_arch_type == MACH_TYPE_REA_2D) +#else +# define machine_is_rea_2d() (0) +#endif + +#ifdef CONFIG_MACH_TI3E524 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TI3E524 +# endif +# define machine_is_eti3e524() (machine_arch_type == MACH_TYPE_TI3E524) +#else +# define machine_is_eti3e524() (0) +#endif + +#ifdef CONFIG_MACH_ATEB9200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATEB9200 +# endif +# define machine_is_ateb9200() (machine_arch_type == MACH_TYPE_ATEB9200) +#else +# define machine_is_ateb9200() (0) +#endif + +#ifdef CONFIG_MACH_AUCKLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AUCKLAND +# endif +# define machine_is_auckland() (machine_arch_type == MACH_TYPE_AUCKLAND) +#else +# define machine_is_auckland() (0) +#endif + +#ifdef CONFIG_MACH_AK3320M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AK3320M +# endif +# define machine_is_ak3220m() (machine_arch_type == MACH_TYPE_AK3320M) +#else +# define machine_is_ak3220m() (0) +#endif + +#ifdef CONFIG_MACH_DURAMAX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DURAMAX +# endif +# define machine_is_duramax() (machine_arch_type == MACH_TYPE_DURAMAX) +#else +# define machine_is_duramax() (0) +#endif + +#ifdef CONFIG_MACH_N35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_N35 +# endif +# define machine_is_n35() (machine_arch_type == MACH_TYPE_N35) +#else +# define machine_is_n35() (0) +#endif + +#ifdef CONFIG_MACH_PRONGHORN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PRONGHORN +# endif +# define machine_is_pronghorn() (machine_arch_type == MACH_TYPE_PRONGHORN) +#else +# define machine_is_pronghorn() (0) +#endif + +#ifdef CONFIG_MACH_FUNDY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUNDY +# endif +# define machine_is_fundy() (machine_arch_type == MACH_TYPE_FUNDY) +#else +# define machine_is_fundy() (0) +#endif + +#ifdef CONFIG_MACH_LOGICPD_PXA270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOGICPD_PXA270 +# endif +# define machine_is_logicpd_pxa270() (machine_arch_type == MACH_TYPE_LOGICPD_PXA270) +#else +# define machine_is_logicpd_pxa270() (0) +#endif + +#ifdef CONFIG_MACH_CPU777 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPU777 +# endif +# define machine_is_cpu777() (machine_arch_type == MACH_TYPE_CPU777) +#else +# define machine_is_cpu777() (0) +#endif + +#ifdef CONFIG_MACH_SIMICON9201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMICON9201 +# endif +# define machine_is_simicon9201() (machine_arch_type == MACH_TYPE_SIMICON9201) +#else +# define machine_is_simicon9201() (0) +#endif + +#ifdef CONFIG_MACH_LEAP2_HPM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEAP2_HPM +# endif +# define machine_is_leap2_hpm() (machine_arch_type == MACH_TYPE_LEAP2_HPM) +#else +# define machine_is_leap2_hpm() (0) +#endif + +#ifdef CONFIG_MACH_CM922TXA10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM922TXA10 +# endif +# define machine_is_cm922txa10() (machine_arch_type == MACH_TYPE_CM922TXA10) +#else +# define machine_is_cm922txa10() (0) +#endif + +#ifdef CONFIG_MACH_PXA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PXA +# endif +# define machine_is_sandgate() (machine_arch_type == MACH_TYPE_PXA) +#else +# define machine_is_sandgate() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2 +# endif +# define machine_is_sandgate2() (machine_arch_type == MACH_TYPE_SANDGATE2) +#else +# define machine_is_sandgate2() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2G +# endif +# define machine_is_sandgate2g() (machine_arch_type == MACH_TYPE_SANDGATE2G) +#else +# define machine_is_sandgate2g() (0) +#endif + +#ifdef CONFIG_MACH_SANDGATE2P +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANDGATE2P +# endif +# define machine_is_sandgate2p() (machine_arch_type == MACH_TYPE_SANDGATE2P) +#else +# define machine_is_sandgate2p() (0) +#endif + +#ifdef CONFIG_MACH_FRED_JACK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FRED_JACK +# endif +# define machine_is_fred_jack() (machine_arch_type == MACH_TYPE_FRED_JACK) +#else +# define machine_is_fred_jack() (0) +#endif + +#ifdef CONFIG_MACH_TTG_COLOR1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TTG_COLOR1 +# endif +# define machine_is_ttg_color1() (machine_arch_type == MACH_TYPE_TTG_COLOR1) +#else +# define machine_is_ttg_color1() (0) +#endif + +#ifdef CONFIG_MACH_NXEB500HMI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NXEB500HMI +# endif +# define machine_is_nxeb500hmi() (machine_arch_type == MACH_TYPE_NXEB500HMI) +#else +# define machine_is_nxeb500hmi() (0) +#endif + +#ifdef CONFIG_MACH_NETDCU8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETDCU8 +# endif +# define machine_is_netdcu8() (machine_arch_type == MACH_TYPE_NETDCU8) +#else +# define machine_is_netdcu8() (0) +#endif + +#ifdef CONFIG_MACH_ML675050_CPU_BOA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ML675050_CPU_BOA +# endif +# define machine_is_ml675050_cpu_boa() (machine_arch_type == MACH_TYPE_ML675050_CPU_BOA) +#else +# define machine_is_ml675050_cpu_boa() (0) +#endif + +#ifdef CONFIG_MACH_NG_FVX538 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NG_FVX538 +# endif +# define machine_is_ng_fvx538() (machine_arch_type == MACH_TYPE_NG_FVX538) +#else +# define machine_is_ng_fvx538() (0) +#endif + +#ifdef CONFIG_MACH_NG_FVS338 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NG_FVS338 +# endif +# define machine_is_ng_fvs338() (machine_arch_type == MACH_TYPE_NG_FVS338) +#else +# define machine_is_ng_fvs338() (0) +#endif + +#ifdef CONFIG_MACH_PNX4103 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNX4103 +# endif +# define machine_is_pnx4103() (machine_arch_type == MACH_TYPE_PNX4103) +#else +# define machine_is_pnx4103() (0) +#endif + +#ifdef CONFIG_MACH_HESDB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HESDB +# endif +# define machine_is_hesdb() (machine_arch_type == MACH_TYPE_HESDB) +#else +# define machine_is_hesdb() (0) +#endif + +#ifdef CONFIG_MACH_XSILO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XSILO +# endif +# define machine_is_xsilo() (machine_arch_type == MACH_TYPE_XSILO) +#else +# define machine_is_xsilo() (0) +#endif + +#ifdef CONFIG_MACH_ESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESPRESSO +# endif +# define machine_is_espresso() (machine_arch_type == MACH_TYPE_ESPRESSO) +#else +# define machine_is_espresso() (0) +#endif + +#ifdef CONFIG_MACH_EMLC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMLC +# endif +# define machine_is_emlc() (machine_arch_type == MACH_TYPE_EMLC) +#else +# define machine_is_emlc() (0) +#endif + +#ifdef CONFIG_MACH_SISTERON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SISTERON +# endif +# define machine_is_sisteron() (machine_arch_type == MACH_TYPE_SISTERON) +#else +# define machine_is_sisteron() (0) +#endif + +#ifdef CONFIG_MACH_RX1950 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RX1950 +# endif +# define machine_is_rx1950() (machine_arch_type == MACH_TYPE_RX1950) +#else +# define machine_is_rx1950() (0) +#endif + +#ifdef CONFIG_MACH_TSC_VENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TSC_VENUS +# endif +# define machine_is_tsc_venus() (machine_arch_type == MACH_TYPE_TSC_VENUS) +#else +# define machine_is_tsc_venus() (0) +#endif + +#ifdef CONFIG_MACH_DS101J +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DS101J +# endif +# define machine_is_ds101j() (machine_arch_type == MACH_TYPE_DS101J) +#else +# define machine_is_ds101j() (0) +#endif + +#ifdef CONFIG_MACH_MXC30030ADS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MXC30030ADS +# endif +# define machine_is_mxc300_30ads() (machine_arch_type == MACH_TYPE_MXC30030ADS) +#else +# define machine_is_mxc300_30ads() (0) +#endif + +#ifdef CONFIG_MACH_FUJITSU_WIMAXSOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FUJITSU_WIMAXSOC +# endif +# define machine_is_fujitsu_wimaxsoc() (machine_arch_type == MACH_TYPE_FUJITSU_WIMAXSOC) +#else +# define machine_is_fujitsu_wimaxsoc() (0) +#endif + +#ifdef CONFIG_MACH_DUALPCMODEM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DUALPCMODEM +# endif +# define machine_is_dualpcmodem() (machine_arch_type == MACH_TYPE_DUALPCMODEM) +#else +# define machine_is_dualpcmodem() (0) +#endif + +#ifdef CONFIG_MACH_GESBC9312 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GESBC9312 +# endif +# define machine_is_gesbc9312() (machine_arch_type == MACH_TYPE_GESBC9312) +#else +# define machine_is_gesbc9312() (0) +#endif + /* * These have not yet been registered */ diff -ru u-boot-1.1.6.orig/include/lcd.h u-boot-1.1.6/include/lcd.h --- u-boot-1.1.6.orig/include/lcd.h 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/include/lcd.h 2007-01-16 14:44:09.000000000 +0100 @@ -77,7 +77,7 @@ extern vidinfo_t panel_info; -#elif defined CONFIG_PXA250 +#elif (defined CONFIG_PXA250 || defined CONFIG_PXA27X) /* * PXA LCD DMA descriptor */ diff -ru u-boot-1.1.6.orig/lib_arm/board.c u-boot-1.1.6/lib_arm/board.c --- u-boot-1.1.6.orig/lib_arm/board.c 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/lib_arm/board.c 2007-01-16 14:51:11.000000000 +0100 @@ -146,6 +146,14 @@ return (0); } +#if defined (CONFIG_BOARDINFO) +static int show_boardinfo (void) +{ + printf("Board: %s\n",CONFIG_BOARDINFO); + return 0; +} +#endif + /* * WARNING: this code looks "cleaner" than the PowerPC version, but * has the disadvantage that you either get nothing, or everything. @@ -228,6 +236,9 @@ #if defined(CONFIG_DISPLAY_BOARDINFO) checkboard, /* display board info */ #endif +#if defined (CONFIG_BOARDINFO) + show_boardinfo, +#endif dram_init, /* configure available RAM banks */ display_dram_config, NULL, diff -ru u-boot-1.1.6.orig/Makefile u-boot-1.1.6/Makefile --- u-boot-1.1.6.orig/Makefile 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6/Makefile 2007-01-16 14:44:09.000000000 +0100 @@ -122,10 +122,10 @@ CROSS_COMPILE = else ifeq ($(ARCH),ppc) -CROSS_COMPILE = powerpc-linux- +CROSS_COMPILE = powerpc-unknown-linux-gnu- endif ifeq ($(ARCH),arm) -CROSS_COMPILE = arm-linux- +CROSS_COMPILE = arm-softfloat-linux-gnu- endif ifeq ($(ARCH),i386) ifeq ($(HOSTARCH),i386) @@ -220,7 +220,6 @@ # The "tools" are needed early, so put this first # Don't include stuff already done in $(LIBS) SUBDIRS = tools \ - examples \ post \ post/cpu .PHONY : $(SUBDIRS) @@ -2016,6 +2015,9 @@ pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +phycore_pxa270_config : unconfig + @./mkconfig $(@:_config=) arm pxa phycore_pxa270 + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 Index: board/phycore_pxa270/config.mk =================================================================== --- /dev/null +++ b/board/phycore_pxa270/config.mk @@ -0,0 +1,10 @@ +# +# This is config used for compilation of WEP EP250 sources +# +# You might change location of U-Boot in memory by setting right TEXT_BASE. +# This allows for example having one copy located at the end of ram and stored +# in flash device and later on while developing use other location to test +# the code in RAM device only. +# + +TEXT_BASE = 0xa1fd0000 Index: board/phycore_pxa270/lowlevel_init.S =================================================================== --- /dev/null +++ b/board/phycore_pxa270/lowlevel_init.S @@ -0,0 +1,466 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CFG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CFG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CFG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CFG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CFG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CFG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CFG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CFG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CFG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CFG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CFG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CFG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K2FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CFG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + orr r4, r4, #MDREFR_K2FREE + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CFG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 µsec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CFG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CFG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + +setvoltage: + + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CFG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CFG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] + + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: Other boards wait here for the pll to become stable */ + /* I think the pll can do without us (sha) */ + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: +#if 0 + ldr r0,=GPDR2 + ldr r1,=CFG_GPDR2_VAL + and r1,r1,#0xFBFFFFFF /* switch off LED0 (GPIO 90) */ + str r1,[r0] +#endif + mov pc, lr Index: board/phycore_pxa270/Makefile =================================================================== --- /dev/null +++ b/board/phycore_pxa270/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o pcmcia.o mmc.o flash.o +SOBJS := lowlevel_init.o pxavoltage.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Index: board/phycore_pxa270/mmc.c =================================================================== --- /dev/null +++ b/board/phycore_pxa270/mmc.c @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2005 + * Juergen Kilb, Phytec Messtechnik GmbH, armlinux@phytec.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "phycore_pxa270.h" + +void mmc_power_on(void) +{ + /* MMC2 Power at PCM985 */ + __PHYCORE_PXA270_CTRL_REG(PHYCORE_PXA270_CTRL_PHYS + PHYCORE_PXA270_CTRL_REG5) = + PHYCORE_PXA270_CTRL_MMC2PWR + PHYCORE_PXA270_CTRL_MMC2LED; + +} \ No newline at end of file Index: board/phycore_pxa270/phycore_pxa270.c =================================================================== --- /dev/null +++ b/board/phycore_pxa270/phycore_pxa270.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include +#include "phycore_pxa270.h" + +int board_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + + icache_enable(); + + gd->bd->bi_arch_number = MACH_TYPE_PCM027; + gd->bd->bi_boot_params = 0xa0000100; + gd->bd->bi_baudrate = CONFIG_BAUDRATE; +#if (PHYCORE_PXA270_USE_IDE==1) + /* IDE Drive */ + /* Enable IDE Latches */ + __PHYCORE_PXA270_IDE_PLD_REG(PHYCORE_PXA270_IDE_PLD_PHYS + PHYCORE_PXA270_IDE_PLD_REG3) = + PHYCORE_PXA270_IDE_IDEOE + PHYCORE_PXA270_IDE_IDEON + PHYCORE_PXA270_IDE_IDEIN; + + /* Enable Power */ + __PHYCORE_PXA270_IDE_PLD_REG(PHYCORE_PXA270_IDE_PLD_PHYS + PHYCORE_PXA270_IDE_PLD_REG4) = + PHYCORE_PXA270_IDE_PWRENA; + + /* Some harddisks need some time for it's initialization. + * Therefore the next delay of 5s. */ +#endif + +#if (PHYCORE_PXA270_USE_LCD==1) + /* LCD Display */ + /* Enable LCD and Power */ + __PHYCORE_PXA270_CTRL_REG(PHYCORE_PXA270_CTRL_PHYS + PHYCORE_PXA270_CTRL_REG3) = + PHYCORE_PXA270_CTRL_LCDPWR + PHYCORE_PXA270_CTRL_LCDON; +#endif + return 0; +} + +/** + * i2c_init_board - reset i2c bus. When the board is powercycled during a + * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. + * The Phytec board has GPIO117 connected to SCLK which can be toggled + * until all chips think that their current cycles are finished. + */ +int i2c_init_board(void) +{ + int i, icr; + + /* disable I2C controller first, otherwhise it thinks we want to */ + /* talk to the slave port... */ + icr = ICR; + ICR &= ~(ICR_SCLE | ICR_IUE); + + /* set gpio pin low _before_ we change direction to output */ + GPCR(117) = GPIO_bit(117); + + /* now toggle between output=low and high-impedance */ + for (i = 0; i < 20; i++) { + GPDR(117) |= GPIO_bit(117); /* output */ + udelay(10); + GPDR(117) &= ~GPIO_bit(117); /* input */ + udelay(10); + } + + ICR = icr; + + return 0; +} + +int board_late_init(void) +{ + setenv ("stdout","serial"); + setenv ("stdout","serial"); + return 0; +} + +int dram_init( void ){ + DECLARE_GLOBAL_DATA_PTR; + +#if ( CONFIG_NR_DRAM_BANKS > 0 ) + gd->bd->bi_dram[0].start = CFG_SDRAM_1; + gd->bd->bi_dram[0].size = CFG_SDRAM_1_SIZE; +#endif +#if ( CONFIG_NR_DRAM_BANKS > 1 ) + gd->bd->bi_dram[1].start = CFG_SDRAM_2; + gd->bd->bi_dram[1].size = CFG_SDRAM_2_SIZE; +#endif + + return 0; +} + Index: board/phycore_pxa270/phycore_pxa270.h =================================================================== --- /dev/null +++ b/board/phycore_pxa270/phycore_pxa270.h @@ -0,0 +1,262 @@ +/* + * linux/include/asm-arm/arch-pxa/phycore_pxa270.h + * + * (c) 2003 Phytec Messtechnik GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/* + * GPIOs Interrupt Source + */ +//#define GPIO_PHYCORE_PXA270_RTC 0 /* GPIO-0 bei Baseboard über GPIO 1 WAKEUP erreichbar */ +#define GPIO_PHYCORE_PXA270_WAKEUP 1 /* GPIO-1 INT-24 */ +#define GPIO_PHYCORE_PXA270_ETH 2 /* GPIO-2 INT-25 */ +#define GPIO_PHYCORE_PXA270_USB_INT1 3 /* GPIO-3 INT-26 */ +#define GPIO_PHYCORE_PXA270_USB_INT2 4 /* GPIO-4 INT-27 */ +#define GPIO_PHYCORE_PXA270_CAN 5 /* GPIO-5 INT-28 */ +#define GPIO_PCM990_CAN0 83 /* GPIO-82 INT-106 */ +#define GPIO_PCM990_CAN1 81 /* GPIO-81 INT-104 */ + +#define GPIO_PHYCORE_PXA270_CTRL_INT 7 /* GPIO-7 INT-30 */ + +#define GPIO_PHYCORE_PXA270_AC97 10 /* GPIO-10 INT-33 */ +#define GPIO_PHYCORE_PXA270_CF 11 /* GPIO-11 INT-34 */ + +#define GPIO_PHYCORE_PXA270_IDE 13 /* GPIO-13 INT-36 */ +#define GPIO_PHYCORE_PXA270_CTRL_PWR 14 /* GPIO-14 INT-37 */ + +/* + * ethernet chip (SMSC91C111) + */ +#define PHYCORE_PXA270_ETH_PHYS PXA_CS5_PHYS +#define PHYCORE_PXA270_ETH_BASE (0xf0000000) /* phys 0x14000000 */ +#define PHYCORE_PXA270_ETH_SIZE (1*1024*1024) +#define PHYCORE_PXA270_ETH_IRQ IRQ_GPIO(GPIO_PHYCORE_PXA270_ETH) +#define PHYCORE_PXA270_ETH_IRQ_EDGE GPIO_RISING_EDGE + +/* + * Control PLD Regs + */ + +#define PHYCORE_PXA270_CTRL_PHYS 0x04000000 //16-Bit +#define PHYCORE_PXA270_CTRL_SIZE (1*1024*1024) +#define PHYCORE_PXA270_CTRL_INT_IRQ IRQ_GPIO(GPIO_PHYCORE_PXA270_CTRL_INT) +#define PHYCORE_PXA270_CTRL_PWR_IRQ IRQ_GPIO(GPIO_PHYCORE_PXA270_CTRL_PWR) +#define PHYCORE_PXA270_CTRL_IRQ_EDGE GPIO_FALLING_EDGE + +//#define PHYCORE_PXA270_CTRL_REG0 0x00000000 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ ^[C +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG1 0x00000002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG2 0x00000004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +#define PHYCORE_PXA270_CTRL_REG3 0x00000006 /* LCD CTRL REGISTER 3 */ +#define PHYCORE_PXA270_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ +#define PHYCORE_PXA270_CTRL_LCDON 0x0002 /* RW LCD Latch on */ +#define PHYCORE_PXA270_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ +#define PHYCORE_PXA270_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ +#define PHYCORE_PXA270_CTRL_REG4 0x00000008 /* MMC1 CTRL REGISTER 4 */ +#define PHYCORE_PXA270_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* R=0 not used */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* R=0 not used */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* R=0 not used */ +#define PHYCORE_PXA270_CTRL_REG5 0x0000000A /* MMC2 CTRL REGISTER 5 */ +#define PHYCORE_PXA270_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */ +#define PHYCORE_PXA270_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */ +#define PHYCORE_PXA270_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */ +#define PHYCORE_PXA270_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */ +//#define PHYCORE_PXA270_CTRL_REG6 0x0000000C /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG7 0x0000000E /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG8 0x00000010 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG9 0x00000012 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG10 0x00000014 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG11 0x00000016 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG12 0x00000018 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG13 0x0000001A /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG14 0x0000001C /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0001 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0002 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0004 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_ 0x0008 /* RESET REGISTER */ +//#define PHYCORE_PXA270_CTRL_REG15 0x0000001E /* RESET REGISTER */ + + +#define __PHYCORE_PXA270_CTRL_REG(x) (*((volatile unsigned char *)(x))) + +/* + * IDE + */ + +#define PHYCORE_PXA270_IDE_IRQ IRQ_GPIO(GPIO_PHYCORE_PXA270_IDE) +#define PHYCORE_PXA270_IDE_IRQ_EDGE GPIO_RISING_EDGE + +#define PHYCORE_PXA270_IDE_PLD_PHYS 0x20000000 /* 16-Bit Zugriff */ +#define PHYCORE_PXA270_IDE_PLD_BASE 0xf6000000 +#define PHYCORE_PXA270_IDE_PLD_SIZE (1*1024*1024) + +#define PHYCORE_PXA270_IDE_PLD_REG0 0x00001000 /* OFFSET IDE REGISTER 0 */ +/*#define PHYCORE_PXA270_IDE_ 0x0001*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_ 0x0002*/ /* R=0 not used */ +#define PHYCORE_PXA270_IDE_PM5V 0x0004 /* R System VCC_5V */ +#define PHYCORE_PXA270_IDE_STBY 0x0008 /* R System StandBy */ + +#define PHYCORE_PXA270_IDE_PLD_REG1 0x00001002 /* OFFSET IDE REGISTER 1 */ +#define PHYCORE_PXA270_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */ +/*#define PHYCORE_PXA270_IDE_ 0x0002*/ /* R=0 not used */ +#define PHYCORE_PXA270_IDE_DMAENA 0x0004 /* RW DMA Enable */ +#define PHYCORE_PXA270_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */ + +#define PHYCORE_PXA270_IDE_PLD_REG2 0x00001004 /* OFFSET IDE REGISTER 2 */ +#define PHYCORE_PXA270_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */ +#define PHYCORE_PXA270_IDE_RES 0x0002 /* RW IDE Reset Bit */ +/*#define PHYCORE_PXA270_IDE_ 0x0004*/ /* R=0 */ +#define PHYCORE_PXA270_IDE_RDY 0x0008 /* RDY */ + +#define PHYCORE_PXA270_IDE_PLD_REG3 0x00001006 /* OFFSET IDE REGISTER 3 */ +#define PHYCORE_PXA270_IDE_IDEOE 0x0001 /* RW Latch on Databus */ +#define PHYCORE_PXA270_IDE_IDEON 0x0002 /* RW Latch on Control Address */ +#define PHYCORE_PXA270_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */ +/*#define PHYCORE_PXA270_IDE_ 0x0008*/ /* R=0 not used */ + +#define PHYCORE_PXA270_IDE_PLD_REG4 0x00001008 /* OFFSET IDE REGISTER 4 */ +#define PHYCORE_PXA270_IDE_PWRENA 0x0001 /* RW IDE Power enable */ +#define PHYCORE_PXA270_IDE_5V 0x0002 /* R IDE Power 5V */ +/*#define PHYCORE_PXA270_IDE_ 0x0004*/ /* R=0 not used */ +#define PHYCORE_PXA270_IDE_PWG 0x0008 /* R IDE Power is on */ + +/*#define PHYCORE_PXA270_IDE_PLD_REG5 0x0000100E*/ /* OFFSET IDE REGISTER 5 */ +/*#define PHYCORE_PXA270_IDE_REG5_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG5_ 0x0008*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG5_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG5_ 0x0008*/ /* R=0 not used */ + +/*#define PHYCORE_PXA270_IDE_PLD_REG6 0x00001010*/ /* OFFSET IDE REGISTER 6 */ +/*#define PHYCORE_PXA270_IDE_REG6_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG6_ 0x0008*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG6_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG6_ 0x0008*/ /* R=0 not used */ + +/*#define PHYCORE_PXA270_IDE_PLD_REG7 0x00001012*/ /* OFFSET IDE REGISTER 7 */ +/*#define PHYCORE_PXA270_IDE_REG7_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG7_ 0x0008*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG7_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_IDE_REG7_ 0x0008*/ /* R=0 not used */ + + +#define __PHYCORE_PXA270_IDE_PLD_REG(x) (*((volatile unsigned char *)(x))) + +/* + * Compact Flash + */ +#define PHYCORE_PXA270_CF_IRQ IRQ_GPIO(GPIO_PHYCORE_PXA270_CF) +#define PHYCORE_PXA270_CF_IRQ_EDGE GPIO_RISING_EDGE + + +#define PHYCORE_PXA270_CF_PLD_PHYS 0x30001000 //16-Bit +#define PHYCORE_PXA270_CF_PLD_SIZE (1*1024*1024) + +#define PHYCORE_PXA270_CF_PLD_REG0 0x00000000 /* OFFSET CF REGISTER 0 */ +#define PHYCORE_PXA270_CF_REG0_LED 0x0001 /* RW LED an */ +#define PHYCORE_PXA270_CF_REG0_BLK 0x0002 /* RW LED Blink bei Zugriff */ +#define PHYCORE_PXA270_CF_REG0_PM5V 0x0004 /* R System VCC_5V an */ +#define PHYCORE_PXA270_CF_REG0_STBY 0x0008 /* R System StandBy */ + +#define PHYCORE_PXA270_CF_PLD_REG1 0x00000002 /* OFFSET CF REGISTER 1 */ +#define PHYCORE_PXA270_CF_REG1_IDEMODE 0x0001 /* RW CF-Card als TrueIDE */ +#define PHYCORE_PXA270_CF_REG1_CF0 0x0002 /* RW CF-Card auf ADDR 0x28000000 */ +/*#define PHYCORE_PXA270_CF_REG1_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_CF_REG1_ 0x0008*/ /* R=0 not used */ + +#define PHYCORE_PXA270_CF_PLD_REG2 0x00000004 /* OFFSET CF REGISTER 2 */ +#define PHYCORE_PXA270_CF_REG2_RESENA 0x0001 /* RW CF RESET BIT Enable */ +#define PHYCORE_PXA270_CF_REG2_RES 0x0002 /* RW CF RESET BIT */ +#define PHYCORE_PXA270_CF_REG2_RDYENA 0x0004 /* RW Enabele CF_RDY */ +#define PHYCORE_PXA270_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */ + +#define PHYCORE_PXA270_CF_PLD_REG3 0x00000006 /* OFFSET CF REGISTER 3 */ +#define PHYCORE_PXA270_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */ +#define PHYCORE_PXA270_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */ +#define PHYCORE_PXA270_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */ +#define PHYCORE_PXA270_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */ + +#define PHYCORE_PXA270_CF_PLD_REG4 0x00000008 /* OFFSET CF REGISTER 4 */ +#define PHYCORE_PXA270_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */ +#define PHYCORE_PXA270_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */ +#define PHYCORE_PXA270_CF_REG4_3B 0x0004 /* RW 3.0V Backup aus VCC (5_3V=0) */ +#define PHYCORE_PXA270_CF_REG4_PWG 0x0008 /* R CF-Power is on */ + +#define PHYCORE_PXA270_CF_PLD_REG5 0x0000000A /* OFFSET CF REGISTER 5 */ +#define PHYCORE_PXA270_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */ +#define PHYCORE_PXA270_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */ +#define PHYCORE_PXA270_CF_REG5_VS1 0x0004 /* R CF /VS1 */ +#define PHYCORE_PXA270_CF_REG5_VS2 0x0008 /* R CF /VS2 */ + +#define PHYCORE_PXA270_CF_PLD_REG6 0x0000000C /* OFFSET CF REGISTER 6 */ +#define PHYCORE_PXA270_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */ +#define PHYCORE_PXA270_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */ +/*#define PHYCORE_PXA270_CF_REG1_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_CF_REG1_ 0x0008*/ /* R=0 not used */ + +/*#define PHYCORE_PXA270_CF_PLD_REG7 0x0000000E*/ /* OFFSET CF REGISTER 7 */ +/*#define PHYCORE_PXA270_CF_REG7_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_CF_REG7_ 0x0008*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_CF_REG7_ 0x0004*/ /* R=0 not used */ +/*#define PHYCORE_PXA270_CF_REG7_ 0x0008*/ /* R=0 not used */ + + +#define __PHYCORE_PXA270_CF_PLD_REG(x) (*((volatile unsigned char *)(x))) + Index: board/phycore_pxa270/pcmcia.c =================================================================== --- /dev/null +++ b/board/phycore_pxa270/pcmcia.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "phycore_pxa270.h" + +void pcmcia_power_on(void) +{ + /* CF Drive */ + /* switch to true-IDE Mode */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG1) = + PHYCORE_PXA270_CF_REG1_IDEMODE; + /* reset CF-Card */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG2) = + PHYCORE_PXA270_CF_REG2_RESENA + PHYCORE_PXA270_CF_REG2_RES;; + /* Enable Power */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG4) = + PHYCORE_PXA270_CF_REG4_PWRENA; + /* Enable CF Latches */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG3) = + PHYCORE_PXA270_CF_REG3_CFOE + PHYCORE_PXA270_CF_REG3_CFON + + PHYCORE_PXA270_CF_REG3_CFIN + PHYCORE_PXA270_CF_REG3_CFCD; + + /* release reset from CF-Card */ + udelay(10000); + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG2) = + PHYCORE_PXA270_CF_REG2_RESENA; + udelay(10000); +} + +void pcmcia_power_off(void) +{ + /* CF Drive */ + /* reset CF-Card */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG2) = + PHYCORE_PXA270_CF_REG2_RESENA + PHYCORE_PXA270_CF_REG2_RES;; + /* Disable CF Latches */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG3) = 0; + /* Disable Power */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG4) = 0; +} + +void ide_led(uchar led, uchar status) +{ + if (status) + { + /* CF-Led on */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG0) = 1; + } else + { + /* CF-Led off */ + __PHYCORE_PXA270_CF_PLD_REG(PHYCORE_PXA270_CF_PLD_PHYS + PHYCORE_PXA270_CF_PLD_REG0) = 0; + } +} \ No newline at end of file Index: board/phycore_pxa270/pxavoltage.S =================================================================== --- /dev/null +++ b/board/phycore_pxa270/pxavoltage.S @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#define LTC1663_ADDR 0x0C + +#define VOLT_1_50 0x0D /* DAC value for 1.50V */ + + .global initPXAvoltage + +@ Set the voltage to 1.55V early in the boot process so we can run +@ at a high clock speed and boot quickly. Note that this is necessary +@ because the reset button does not reset the CPU voltage, so if the +@ voltage was low (say 0.85V) then the CPU would crash without this +@ routine + +@ This routine clobbers r0-r4 + +initializei2c: + + ldr r2, =CKEN + ldr r3, [r2] + orr r3, r3, #CKEN15_PWRI2C + str r3, [r2] + + ldr r2, =PCFR + ldr r3, [r2] + orr r3, r3, #PCFR_PI2C_EN + str r3, [r2] + + /* delay for about 250msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0000 +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + /* end delay */ + + ldr r0, =PWRICR + ldr r1, [r0] + bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP) + str r1, [r0] + + orr r1, r1, #ICR_UR /* Reset Pi2C Unit */ + str r1, [r0] + + ldr r2, =PWRISR /* clear all interrupts */ + ldr r3, =0x7ff + str r3, [r2] + + bic r1, r1, #ICR_UR /* clear PI2C reset bit in PWRICR (r0) */ + str r1, [r0] + + mov r1, #(ICR_GCD | ICR_SCLE) /* disable general call and enable SCL */ + str r1, [r0] + + orr r1, r1, #ICR_IUE /* enable PI2C unit */ + str r1, [r0] + + orr r1, r1, #ICR_FM /* use 160kbps */ + str r1, [r0] + + /* delay for about 1msec + */ + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC00 @11,32msec + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + /* end delay */ + + mov pc, lr + +sendbytei2c: + ldr r3, =PWRIDBR + str r0, [r3] + ldr r3, =PWRICR + ldr r0, [r3] + orr r0, r0, r1 + bic r0, r0, r2 + str r0, [r3] + orr r0, r0, #ICR_TB + str r0, [r3] + + mov r2, #0x100 + +waitfortxemptyi2c: + + ldr r0, =PWRISR + ldr r1, [r0] + + /* take it from the top if we don't get empty after a while */ + subs r2, r2, #1 + moveq lr, r4 + beq initPXAvoltage + + tst r1, #ISR_ITE + + beq waitfortxemptyi2c + + orr r1, r1, #ISR_ITE + str r1, [r0] + + mov pc, lr + +initPXAvoltage: + + mov r4, lr + + bl initializei2c + + /* now send the real message to set the correct voltage */ + ldr r0, =LTC1663_ADDR + mov r0, r0, LSL #1 + mov r1, #ICR_START /* set bits in ICR */ + ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK) /* clear Bits in ICR */ + bl sendbytei2c + + ldr r0, =VOLT_1_50 + and r0, r0, #0xff + ldr r1, =(ICR_STOP | ICR_ALDIE) + mov r2, #ICR_START + bl sendbytei2c + + ldr r0,=GPDR2 + ldr r1,=CFG_GPDR2_VAL + and r1,r1,#0xFBFFFFFF /* switch off LED0 (GPIO 90) */ + str r1,[r0] + + @ delay a little for the volatage to stablize + ldr r3, =OSCR + mov r2, #0 + str r2, [r3] + ldr r1, =0xC0c + +1: + ldr r2, [r3] + cmp r1, r2 + bgt 1b + mov pc, r4 + Index: board/phycore_pxa270/u-boot.lds =================================================================== --- /dev/null +++ b/board/phycore_pxa270/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: include/configs/phycore_pxa270.h =================================================================== --- /dev/null +++ b/include/configs/phycore_pxa270.h @@ -0,0 +1,901 @@ +/* + * Copyright (C) 2005 Phytec Messtechnik GmbH + * Juergen Kilb, H. Klaholz + * + * Copyright (C) 2006 Pengutronix + * Sascha Hauer + * Robert Schwebel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_BOARDINFO "Phytec phyCORE-pxa270" + +/* + * phyCORE-PXA270 configuration settings + * Set these to 0/1 to enable or disable the features. + */ + +#define PHYCORE_PXA270_USE_LCD 1 +#define PHYCORE_PXA270_USE_MMC 1 +#define PHYCORE_PXA270_USE_IDE 0 +#define PHYCORE_PXA270_USE_CF 1 +#define PHYCORE_PXA270_USE_FFUART 1 +#define PHYCORE_PXA270_USE_BTUART 1 +#define PHYCORE_PXA270_USE_IRUART 1 +#define PHYCORE_PXA270_USE_AC97 1 +#define PHYCORE_PXA270_USE_SSP 1 +#define PHYCORE_PXA270_USE_SSP3 1 +#define PHYCORE_PXA270_USE_K3FLASH 0 + +/* 260 MHz or 520 MHZ */ +#define PHYCORE_PXA270_SPEED 520 + +/********************************************************************* + * CONFIG PXA270 GPIO settings * + *********************************************************************/ +#if PHYCORE_PXA270_USE_LCD == 1 +/** REG GPSR0 + * GP16 is 1 */ +#define GPSR0_LCD 0x00010000 /* GPIO16 is 1 */ +/** REG GPDR0 + * GP16 == PWM0 is output + ** REG GPDR1 + * GP58 == LDD0 is output + * GP59 == LDD1 is output + * GP60 == LDD2 is output + * GP61 == LDD3 is output + * GP62 == LDD4 is output + * GP63 == LDD5 is output + *** REG GPDR2 + * GP64 == LDD6 is output + * GP65 == LDD7 is output + * GP66 == LDD8 is output + * GP67 == LDD9 is output + * GP68 == LDD10 is output + * GP69 == LDD11 is output + * GP70 == LDD12 is output + * GP71 == LDD13 is output + * GP72 == LDD14 is output + * GP73 == LDD15 is output + * GP74 == LCDFCLK is output + * GP75 == LCDLCLK is output + * GP76 == LCDPCLK is output + * GP77 == LCDBIAS is output */ +#define GPDR0_LCD 0x00010000 /* GPIO 16 Output */ +#define GPDR1_LCD 0xFC000000 /* GPIO 58 - 63 Output */ +#define GPDR2_LCD 0x00003FFF /* GPIO 64 - 77 Output */ +#define GAFR1_U_LCD 0xAAA00000 /* GPIO 58 - 63 AF 02 */ +#define GAFR2_L_LCD 0x0AAAAAAA /* GPIO 64 - 77 AF 02 */ +#else +#define GPDR0_LCD 0x00000000 +#define GPSR0_LCD 0x00000000 +#define GPDR1_LCD 0x00000000 +#define GPDR2_LCD 0x00000000 +#define GAFR1_U_LCD 0x00000000 +#define GAFR2_L_LCD 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_MMC == 1 +/* REG GPDR1 + * GP32 == MMCCLK is output */ +#define GPDR1_MMC 0x00000001 /* GPIO32 is OUTPUT */ +/** REG GAFR1_L + * GP32 == MMCLK is AF10 + ** REG GAFR2_U + * GP92 == MMDAT0 is AF01 + ** REG GAFR3_L + * GP109== MMDAT1 is AF01 + * GP110== MMCS0 is AF01 + * GP111== MMCS1 is AF01 + ** REG GAFR3_U + * GP112== MMCMD is AF01 */ +#define GAFR1_L_MMC 0x00000002 /* GPIO 32 is AF10 */ +#define GAFR2_U_MMC 0x01000000 /* GPIO 92 AF 01 */ +#define GAFR3_L_MMC 0x54000000 /* GPIO 109 - 111 AF 01 */ +#define GAFR3_U_MMC 0x00000001 /* GPIO 112 AF 01 */ +#else +#define GPDR1_MMC 0x00000000 +#define GAFR2_U_MMC 0x00000000 +#define GAFR3_L_MMC 0x00000000 +#define GAFR3_U_MMC 0x00000000 +#endif + +#if ((PHYCORE_PXA270_USE_IDE == 1) || (PHYCORE_PXA270_USE_CF == 1)) +/** REG GPSR1 + * GP48 == nPOE is 1 + * GP49 == nPWE is 1 + * GP50 == nPIOR is 1 + * GP51 == nPIOW is 1 + * GP54 == nPCE2 is 1 + * GP55 == nPREG is 1 + ** REG GPSR2 + * GP85 == nPCE1 is 1 */ +#define GPSR1_IDECF 0x00CF0000 /* GPIO 48-51, 54-55 is 1 */ +#define GPSR2_IDECF 0x00200000 /* GPIO 85 is 1 */ +/* REG GPDR1 + * GP48 == nPOE is output + * GP49 == nPWE is output + * GP50 == nPIOR is output + * GP51 == nPIOW is output + * GP54 == nPCE2 is output + * GP55 == nPREG is output + * REG GPDR2 + * GP79 == PSKTSEL is output + * GP85 == nPCE1 is output */ +#define GPDR1_IDECF 0x00CF0000 /* GPIO 48-51, 54-57 is output */ +#define GPDR2_IDECF 0x00208000 /* GPIO 79,85 is output */ +/** REG GAFR1_U + * GP48 == nPOE is AF10 + * GP49 == nPWE is AF10 + * GP50 == nPIOR is AF10 + * GP51 == nPIOW is AF10 + * GP54 == nPCE2 is AF10 + * GP55 == nPREG is AF10 + * GP56 == nPWAIT is AF01 + * GP57 == nPIOIS16 is AF01 + * REG GAFR2_L + * GP79 == PSKTSEL is AF01 + * REG GAFR2_U + * GP85 == nPCE1 is AF01 */ +#define GAFR1_U_IDECF 0x0005A0AA /* GPIO 48-55 AF 10, 56-57 AF01 */ +#define GAFR2_L_IDECF 0x40000000 /* GPIO 79 AF 01 */ +#define GAFR2_U_IDECF 0x00000400 /* GPIO 85 AF 01 */ +#else +#define GPSR1_IDECF 0x00000000 +#define GPSR2_IDECF 0x00000000 +#define GPDR1_IDECF 0x00000000 +#define GPDR2_IDECF 0x00000000 +#define GAFR1_U_IDECF 0x00000000 +#define GAFR2_L_IDECF 0x00000000 +#define GAFR2_U_IDECF 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_FFUART == 1 +/* REG GPSR1 + * GP41 == FFRTS is 1 */ +#define GPSR1_FFUART 0x00000200 /* GPIO 41 is 1 */ +/* REG GPDR1 + * GP39 == FFTXD is output + * GP40 == FFDTR is output + * GP41 == FFRTS is output */ +#define GPDR1_FFUART 0x00000380 /* GPIO 39-41 is OUTPUT */ +/* REG GAFR1_L + * GP34 == FFRXD is AF01 + * GP35 == FFCTS is AF01 + * GP36 == FFDCD is AF01 + * GP37 == FFDSR is AF01 + * GP38 == FFRI is AF01 + * GP39 == FFTXD is AF10 + * GP40 == FFDTR is AF10 + * GP41 == FFRTS is AF10 */ +#define GAFR1_L_FFUART 0x000A9550 /* GPIO 34-38 is AF01, 39-41 is AF10 */ +#else +#define GPSR1_FFUART 0x00000000 +#define GPDR1_FFUART 0x00000000 +#define GAFR1_L_FFUART 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_BTUART == 1 +/* REG GPSR1 + * GP45 == BTRTS is 1*/ +#define GPSR1_BTUART 0x00002000 /* GPIO 45 is 1 */ +/* REG GPDR1 + * GP43 == BTRXD is output + * GP45 == BTRTS is output */ +#define GPDR1_BTUART 0x00002800 /* GPIO 43,45 is OUTPUT */ +/* REG GAFR1_L + * GP42 == BTRXD is AF01 + * GP43 == BTTXD is AF10 + * GP44 == BTCTS is AF01 + * GP45 == BTRTS is AF10 */ +#define GAFR1_L_BTUART 0x09900000 /* GPIO 42,44 is AF01, 43,45 is AF10 */ +#else +#define GPSR1_BTUART 0x00000000 +#define GPDR1_BTUART 0x00000000 +#define GAFR1_L_BTUART 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_IRUART == 1 +/* REG GPDR1 + * GP47 == STDTXD is output */ +#define GPDR1_IRUART 0x00008000 /* GPIO 47 is OUTPUT */ +/* REG GAFR1_L + * GP46 == STDRXD is AF10 + * GP47 == STDTXD is AF01 */ +#define GAFR1_L_IRUART 0x60000000 /* GPIO 46 is AF10, 47 is AF01 */ +#else +#define GPDR1_IRUART 0x00000000 +#define GAFR1_L_IRUART 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_AC97 == 1 +/* REG GPDR0 + * GP30 == AC97DatO is output + * GP31 == AC97Sync is output + ** REG GPDR3 + * GP113== nAC97_RESET is output */ +#define GPDR0_AC97 0xC0000000 /* GPIO 30,31 is OUTPUT */ +#define GPDR3_AC97 0x00020000 /* GPIO 113 is OUTPUT */ +/* REG GAFR0_L + * GP28 == AC97CLK is AF01 + * GP29 == AC97DatIn is AF01 + * GP30 == AC97DatO is AF10 + * GP31 == AC97SYNC is AF10 + * GP113== AC97_RES is AF10 */ +#define GAFR0_U_AC97 0xA5000000 /* GPIO 28,29 is AF01, 30,31 is AF10 */ +#define GAFR3_U_AC97 0x00000008 /* GPIO 113 is AF10 */ +#else +#define GPDR0_AC97 0x00000000 +#define GPDR3_AC97 0x00000000 +#define GAFR0_U_AC97 0x00000000 +#define GAFR3_U_AC97 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_SSP == 1 +/** REG GPSR0 + * GP24 == SSPSFRM is 1 */ +#define GPSR0_SSP 0x01000000 /* GPIO24 is 1 */ +/* REG GPDR0 + * GP23 == SSPCLK is output + * GP24 == SSPSFRM is output + * GP25 == SSPTXD is output + ** REG GPDR1 + * GP53== SSPSYSCLK is output */ +#define GPDR0_SSP 0x03800000 /* GPIO 23-25 is OUTPUT */ +#define GPDR1_SSP 0x00200000 /* GPIO 53 is OUTPUT */ +/** REG GAFR0_L + * GP23 == SSPSCLK is AF10 + * GP24 == SSPSFRM is AF10 + * GP25 == SSPTXD is AF10 + * GP26 == SSPRXD is AF01 + * GP27 == SSPEXTCLK is AF01 + ** REG GAFR1_U + * GP53 == SSPSYSCLK is AF11 */ +#define GAFR0_U_SSP 0x005A8000 /* GPIO 23-25 is AF10, 26,27 is AF01 */ +#define GAFR1_U_SSP 0x00000C00 /* GPIO 113 is AF10 */ +#else +#define GPSR0_SSP 0x00000000 +#define GPDR0_SSP 0x00000000 +#define GPDR1_SSP 0x00000000 +#define GAFR0_U_SSP 0x00000000 +#define GAFR1_U_SSP 0x00000000 +#endif + +#if PHYCORE_PXA270_USE_SSP3 == 1 +/** REG GPSR2 + * GP83 == SSPSFRM3 is 1 */ +#define GPSR2_SSP3 0x00080000 /* GPIO83 is 1 */ +/* REG GPDR2 + * GP81 == SSPXD3 is output + * GP83 == SSPFRM3 is output + * GP84 == SSPCLK3 is output */ +#define GPDR2_SSP3 0x001A0000 /* GPIO 81,83,84 is OUTPUT */ +/** REG GAFR0_L + * GP81 == SSPTXD3 is AF01 + * GP82 == SSPRXD3 is AF01 + * GP83 == SSPSFRM is AF01 + * GP84 == SSPCLK3 is AF01 */ +#define GAFR2_U_SSP3 0x00000154 /* GPIO 81-84 is AF01 */ +#else +#define GPSR2_SSP3 0x00000000 +#define GPDR2_SSP3 0x00000000 +#define GAFR2_U_SSP3 0x00000000 +#endif + +/* + * GPIO set "1" + * + *** REG GPSR0 + * GP15 == nCS1 is 1 + * GP20 == nSDCS2 is 1 + * GP21 == nSDCS3 is 1 + *** REG GPSR1 + * GP33 == nCS5 is 1 + *** REG GPSR2 + * GP78 == nCS2 is 1 + * GP80 == nCS4 is 1 + */ +#define GPSR0_DFT 0x00308000 +#define GPSR1_DFT 0x00000002 +#define GPSR2_DFT 0x00014000 +#define GPSR3_DFT 0x00000000 + +#define CFG_GPSR0_VAL GPSR0_DFT | GPSR0_LCD | GPSR0_SSP +#define CFG_GPSR1_VAL GPSR1_DFT | GPSR1_IDECF | GPSR1_FFUART | GPSR1_BTUART +#define CFG_GPSR2_VAL GPSR2_DFT | GPSR2_IDECF | GPSR2_SSP3 +#define CFG_GPSR3_VAL GPSR3_DFT + +/* +#define CFG_GPSR0_VAL 0x01308000 +#define CFG_GPSR1_VAL 0x03CFAA82 +#define CFG_GPSR2_VAL 0x00214000 +#define CFG_GPSR3_VAL 0x00000000 +*/ + +/* + * GPIO clear "0" + */ +#define CFG_GPCR0_VAL 0x00000000 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPCR3_VAL 0x00000000 + +/* + * set Direction "1" GPIO == output else input + * + ** REG GPDR0 + * GP03 == PWR_SDA is output + * GP04 == PWR_SCL is output + * GP15 == nCS1 is output + * GP20 == nSDCS2 is output + * GP21 == nSDCS3 is output + ** REG GPDR1 + * GP33 == nCS5 is output + ** REG GPDR2 + * GP78 == nCS2 is output + * GP80 == nCS4 is output + * GP90 == LED0 is output + * GP91 == LED1 is output + ** REG GPDR3 + * GP117== SCL is output + * GP118== SDA is output + */ + +#define GPDR0_DFT 0x00308018 +#define GPDR1_DFT 0x00000002 +#define GPDR2_DFT 0x0C014000 +#define GPDR3_DFT 0x00600000 + +#define CFG_GPDR0_VAL GPDR0_DFT | GPDR0_LCD | GPDR0_AC97 | GPDR0_SSP +#define CFG_GPDR1_VAL GPDR1_DFT | GPDR1_LCD | GPDR1_MMC | GPDR1_IDECF | GPDR1_FFUART | GPDR1_BTUART | GPDR1_IRUART | GPDR1_SSP +#define CFG_GPDR2_VAL GPDR2_DFT | GPDR2_LCD | GPDR2_SSP3 | GPDR2_IDECF +#define CFG_GPDR3_VAL GPDR3_DFT | GPDR3_AC97 + +/* + * set Alternate Funktions + * + ** REG GAFR0_L + * GP15 == nCS1 is AF10 + ** REG GAFR0_U + * GP18 == RDY is AF01 + * GP20 == nSDCS2 is AF01 + * GP21 == nSDCS3 is AF01 + ** REG GAFR1_L + * GP33 == nCS5 is AF10 + ** REG GAFR2_L + * GP78 == nCS2 is AF10 + ** REG GAFR2_U + * GP80 == nCS4 is AF10 + ** REG GAFR3_U + * GP117== SCL is AF01 + * GP118== SDA is AF01 + */ + +#define GAFR0_L_DFT 0x80000000 +#define GAFR0_U_DFT 0x00000510 +#define GAFR1_L_DFT 0x00000008 +#define GAFR1_U_DFT 0x00000000 +#define GAFR2_L_DFT 0x20000000 +#define GAFR2_U_DFT 0x00000002 +#define GAFR3_L_DFT 0x00000000 +#define GAFR3_U_DFT 0x00001400 + +#define CFG_GAFR0_L_VAL GAFR0_L_DFT +#define CFG_GAFR0_U_VAL GAFR0_U_DFT | GAFR0_U_AC97 | GAFR0_U_SSP +#define CFG_GAFR1_L_VAL GAFR1_L_DFT | GAFR1_L_FFUART | GAFR1_L_BTUART | GAFR1_L_IRUART | GAFR1_L_MMC +#define CFG_GAFR1_U_VAL GAFR1_U_DFT | GAFR1_U_LCD | GAFR1_U_IDECF | GAFR1_U_SSP +#define CFG_GAFR2_L_VAL GAFR2_L_DFT | GAFR2_L_LCD | GAFR2_L_IDECF +#define CFG_GAFR2_U_VAL GAFR2_U_DFT | GAFR2_U_IDECF | GAFR2_U_SSP3 | GAFR2_U_MMC +#define CFG_GAFR3_L_VAL GAFR3_L_DFT | GAFR3_L_MMC +#define CFG_GAFR3_U_VAL GAFR3_U_DFT | GAFR3_U_MMC | GAFR3_U_AC97 + +/* +#define CFG_GAFR0_L_VAL 0x90000000 +#define CFG_GAFR0_U_VAL 0xA55A859A +#define CFG_GAFR1_L_VAL 0x699A955A +#define CFG_GAFR1_U_VAL 0xAAA5ACAA +#define CFG_GAFR2_L_VAL 0x6AAAAAAA +#define CFG_GAFR2_U_VAL 0x01000556 +#define CFG_GAFR3_L_VAL 0x54000000 +#define CFG_GAFR3_U_VAL 0x00001549 +*/ + +/* + * Power Manager Sleep Status Register (PSSR) + * + * FIXME: RSC: are these registers set correctly??? + * + * [6] = 0 OTG pad is not holding it's state + * [5] = 1 Read Disable Hold: receivers of all gpio pins are disabled + * [4] = 1 gpio pins are held in their sleep mode state + * [3] = 0 The processor has not been placed in standby mode by + * configuring the PWRMODE register since STS was cleared + * by a reset or by software. + * [2] = 1 nVDD_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [1] = 1 nBATT_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [0] = 1 The processor was placed in sleep mode by configuring the + * PWRMODE register. + */ + +/* #define CFG_PSSR_VAL 0x20 */ +#define CFG_PSSR_VAL 0x37 + + +/********************************************************************* + * CONFIG PXA270 Chipselect settings * + *********************************************************************/ + +/* + * Memory settings + * + * FIXME: RSC: fix documentation + * + * This is the configuration for nCS1/0 -> PLD / flash + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [19] 1 - 16 Bit bus width + * [18:16] 011 - burst RAM or FLASH + * configuration for nCS0 (J3 Flash): + * [15] 0 - Slower Device + * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 0 - 32 Bit bus width + * [02:00] 011 - burst RAM or FLASH + */ +#if PHYCORE_PXA270_USE_K3FLASH == 0 +#define CFG_MSC0_VAL 0x128C1262 +#else +/* configuration for nCS0 (K3 Flash): + * [15] 0 - Slower Device + * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 0 - 32 Bit bus width + * [02:00] 011 - burst RAM or FLASH + */ +#define CFG_MSC0_VAL 0x128C12B3 +#endif + +/* + * This is the configuration for nCS3/2 -> FIXME / FIXME + * configuration for nCS3: POWER + * + * [31] 0 - Slower Device + * [30:28] 111 - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns + * [19] 0 - 32 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: PLD + * [15] 0 - Slower Device + * [14:12] 111 - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC1_VAL 0x128c128c + +/* + * This is the configuration for nCS5/4 -> FIXME / FIXME + * + * configuration for nCS5: LAN Controller + * [31] 0 - Slower Device + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns + * [19] 0 - 32 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS4: USB + * [15] 0 - Slower Device + * [14:12] 111 - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC2_VAL 0x1234128C + +/********************************************************************* + * Configuration for FLASH memory * + *********************************************************************/ + +#define CFG_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CFG_FLASH_SIZE 0x02000000 /* 32 MB */ +#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ +#define CFG_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ +#define CFG_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ +#define CFG_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank */ +#define CFG_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ +#define CFG_FLASH_BASE 0x0000000 /* location of flash memory */ +#if PHYCORE_PXA270_USE_K3FLASH == 1 +#define CFG_FLASH_UNLOCK 1 /* perform hw unlock first */ +#endif +#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* timeout for Erase operation */ +#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* timeout for Write operation */ + +/********************************************************************* + * CONFIG PXA270 SDRAM settings * + *********************************************************************/ + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define CFG_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CFG_DRAM_BASE 0xa0000000 +#define CFG_DRAM_SIZE 0x04000000 + +/* MDCNFG: SDRAM Configuration Register FIXME: RSC: check!! + * + * [31] 0 - Stack1 + * [30] 0 - dcacx2 + * [20] 0 - reserved + * [31:29] 000 - reserved + * [28] 1 - SA1111 compatiblity mode + * [27] 1 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 10 - timings + * [23] 1 - internal banks in lower partition 2/3 (not used) + * [22:21] 10 - row address bits for partition 2/3 (not used) + * [20:19] 01 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15] 0 - Stack1 + * [14] 0 - dcacx0 + * [13] 0 - Stack0 + * [12] 0 - SA1110 compatiblity mode + * [11] 1 - always 1 + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ + +/* K4S561633*/ +#define CFG_MDCNFG_VAL 0x0AC90AC9 + +/* MDREFR: SDRAM Refresh Control Register + * + * [31] 0 - ALTREFA + * [30] 0 - ALTREFB + * [29] 1 - K0DB4 + * [28] 0 - reserved + * [27] 0 - reserved + * [26] 0 - reserved + * [25] 1 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 1 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 0 - APD: no auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 0 - RESERVED + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CFG_MDREFR_VAL 0x2281C018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00020022 + +/********************************************************************* + * CONFIG PXA270 Clock generation * + *********************************************************************/ +#define CFG_FLYCNFG_VAL 0x00010001 +#define CFG_SXCNFG_VAL 0x40044004 +#define CFG_CKEN 0x005002D0 /* Memory, Int.Memory, OS Timer, BTUART, FFUART, STUART */ + +#if PHYCORE_PXA270_SPEED == 520 +#define CFG_CCCR 0x00000290 /* Memory Clock is f. Table; N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */ +#elif PHYCORE_PXA270_SPEED == 260 +#define CFG_CCCR 0x02000288 /* Memory Clock is System-Bus Freq., N=2.5, L=8 => 8x13=104, 104x2,5=260 MHz */ +#else +#error You have specified an illegal speed. +#endif + +/********************************************************************* + * CONFIG PXA270 CF interface * + *********************************************************************/ +#define CFG_MECR_VAL 0x00000003 +#define CFG_MCMEM0_VAL 0x00010504 +#define CFG_MCMEM1_VAL 0x00010504 +#define CFG_MCATT0_VAL 0x00010504 +#define CFG_MCATT1_VAL 0x00010504 +#define CFG_MCIO0_VAL 0x00004715 +#define CFG_MCIO1_VAL 0x00004715 + +/********************************************************************* + * CONFIG PXA270 IDE interface * + *********************************************************************/ +#if ((PHYCORE_PXA270_USE_IDE == 1) || (PHYCORE_PXA270_USE_CF == 1)) +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ATAPI 1 +#define CONFIG_SUPORT_VFAT 1 +#define CONFIG_PXA_PCMCIA 1 +#define CONFIG_PXA_IDE 1 +#undef CONFIG_IDE_LED /* no led supported */ +#define CONFIG_PCMCIA_SLOT_A 1 /* just to keep build system happy */ +#define CFG_PCMCIA_MEM_ADDR 0x38000000 +#define CFG_PCMCIA_MEM_SIZE 0x04000000 + +#if ((PHYCORE_PXA270_USE_IDE == 1) && (PHYCORE_PXA270_USE_CF == 1)) +#define CFG_IDE_MAXBUS 2 /* max. 2 IDE bus */ +#define CFG_IDE_MAXDEVICE 4 /* max. 2 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x20000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_IDE1_OFFSET 0x10000000 +#endif +#if ((PHYCORE_PXA270_USE_IDE == 1) && (PHYCORE_PXA270_USE_CF == 0)) +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x20000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#endif +#if ((PHYCORE_PXA270_USE_IDE == 0) && (PHYCORE_PXA270_USE_CF == 1)) +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ +#define CFG_ATA_BASE_ADDR 0x30000000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#endif + +#define CFG_ATA_DATA_OFFSET 0x0 +#define CFG_ATA_REG_OFFSET 0x0 +#define CFG_ATA_ALT_OFFSET 0x800 +#endif +/********************************************************************* + * CONFIG PXA270 MMC interface * + *********************************************************************/ +#if PHYCORE_PXA270_USE_MMC == 1 +#define CONFIG_MMC 1 +#define CFG_MMC_BASE 0xF0000000 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SUPORT_VFAT 1 +#endif +/********************************************************************* + * CONFIG Ethernet SMSC91C111 * + *********************************************************************/ + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x14000300 /* CHIP Select 5 */ +#define CONFIG_SMC_USE_32_BIT +#undef CONFIG_SMC_91111_EXT_PHY +#define CONFIG_NET_RETRY_COUNT 10 + +#define CONFIG_ETHADDR 00:50:C2:14:43:85 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_IPADDR 192.168.0.2 +#define CONFIG_SERVERIP 192.168.0.1 + +/********************************************************************* + * CONFIG PXA270 LCD * + *********************************************************************/ +#if PHYCORE_PXA270_USE_LCD == 1 +#define CONFIG_LCD +#define CONFIG_SHARP_LQ084V1DG21 +#endif +/********************************************************************* + * CONFIG PXA270 I2C * + *********************************************************************/ +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe + +#define CFG_ENV_IS_IN_EEPROM 1 + +#define CFG_ENV_OFFSET 0x00 /* environment starts here */ +#define CFG_ENV_SIZE 2048 /* 1 KiB */ +#define CFG_I2C_EEPROM_ADDR 0x54 /* A0=0, A1=0 (hardwired) */ + /* without R/W-Bit ! */ +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of byte address */ +#define CFG_EEPROM_SIZE 4096 /* size in bytes */ +#undef CFG_I2C_INIT_BOARD /* board hasn't it's own init */ +#define BOARD_LATE_INIT 1 + + +/* + ##################################################################### + # # + # U-BOOT settings # + # # + ##################################################################### + */ + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Select u-boot PXA270 configuration + */ +#define CONFIG_PXA27X 1 /* this is an PXA270 CPU */ +#define CONFIG_PHYCORE_PXA270 1 /* config for Phytec PCM-027 board */ +#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ + +/* + * Select serial console configuration + */ +#define CONFIG_FFUART 1 /* FFUART is default */ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Select support for RTC PCF8564 (fully comp. to PCF8563 from Philips) + */ +#define CONFIG_RTC_PCF8563 1 +#define CFG_I2C_RTC_ADDR 0x51 +/* + * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if + * neccessary in include/cmd_confdefs.h file. (Un)comment for getting + * functionality or size of u-boot code. + */ +#if ((PHYCORE_PXA270_USE_IDE == 1) || (PHYCORE_PXA270_USE_CF == 1) || (PHYCORE_PXA270_USE_MMC == 1)) +#define CONFIG_STORAGE_COMMANDS CFG_CMD_FAT | CFG_CMD_EXT2 +#endif + +#if ((PHYCORE_PXA270_USE_IDE == 1) || (PHYCORE_PXA270_USE_CF == 1)) +#define CONFIG_IDECF_COMMANDS CFG_CMD_IDE | CFG_CMD_PCMCIA +#endif + +#if (PHYCORE_PXA270_USE_MMC == 1) +#define CONFIG_MMC_COMMANDS CFG_CMD_MMC +#endif + +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_JFFS2 | CFG_CMD_DHCP | \ + CFG_CMD_I2C | CFG_CMD_EEPROM | CFG_CMD_PING | \ + CFG_CMD_DATE | \ + CONFIG_STORAGE_COMMANDS | \ + CONFIG_IDECF_COMMANDS | \ + CONFIG_MMC_COMMANDS ) + +#include + +/* + * low level support for gdb debugger + * + */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Boot options. Setting delay to -1 stops autostart count down. + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" +#define CONFIG_BOOTCOMMAND "" +#undef CONFIG_SHOW_BOOT_PROGRESS +#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process even with bootdelay=0 */ + +/* + * General options for u-boot. Modify to save memory foot print + */ +#define CFG_LONGHELP /* undef saves memory */ +#define CFG_PROMPT "uboot> " /* prompt string */ +#define CFG_CBSIZE 1024 /* console I/O buffer */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ +#define CFG_MAXARGS 16 /* max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ +#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ +#define CFG_MEMTEST_END 0xa0800000 +#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ + +/* phytec */ +// #define CFG_CPUSPEED 0x141 /* core clock - register value */ +#define CFG_CPUSPEED 0x0a000290 /* for 520 MHz */ + +/* + * Definitions related to passing arguments to kernel. + */ +#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ +#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ +#define CONFIG_INITRD_TAG 1 /* send initrd params */ +#undef CONFIG_VFD /* do not send framebuffer setup */ + + +/* + * Malloc pool need to host env + 128 Kb reserve for other allocations. + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10)) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_STACKSIZE (120<<10) /* stack size */ + +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ +#endif + +/* + * This is setting for JFFS2 support in u-boot. + * Right now there is no gain for user, but later on booting kernel might be + * possible. Consider using XIP kernel running from flash to save RAM + * footprint. + * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 5 +#define CFG_JFFS2_NUM_BANKS 1 +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=phys_mapped_flash" +#define MTDPARTS_DEFAULT "mtdparts=phys_mapped_flash:256k(u-boot)ro,1536k(kernel),-(root)" + +/* + * Environment setup. Definitions of monitor location and size with + * definition of environment setup ends up in 2 possibilities. + * 1. Embeded environment - in u-boot code is space for environment + * 2. Environment is read from predefined sector of flash + * Right now we support 2. possiblity, but expecting no env placed + * on mentioned address right now. This also needs to provide whole + * sector for it - for us 256Kb is really waste of memory. U-boot uses + * default env. and until kernel parameters could be sent to kernel + * env. has no sense to us. + */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ +#undef CFG_ENV_IS_IN_FLASH /* we store ENV in EEPROM */ +#define CONFIG_ENV_OVERWRITE /* env is not writable now */ + +/* + * Well this has to be defined, but on the other hand it is used differently + * one may expect. For instance loadb command do not cares :-) + * So advice is - do not relay on this... + */ +#define CFG_LOAD_ADDR 0xa3000000 + +#endif /* __CONFIG_H */ Index: board/phycore_pxa270/flash.c =================================================================== --- /dev/null +++ b/board/phycore_pxa270/flash.c @@ -0,0 +1,318 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( CFG_FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( CFG_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( CFG_FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( CFG_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( CFG_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( CFG_FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( CFG_FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( CFG_FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( CFG_FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + + + +ulong flash_init (void) +{ + int i; + FLASH_BUS address = CFG_FLASH_BASE; + + flash_info[0].size = CFG_FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; +#ifdef CFG_FLASH_UNLOCK + /* Some devices are hw locked after start. */ + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); + flash_ready (0); + *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); +#endif + address += CFG_FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#endif + return CFG_FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} Index: board/phycore_pxa270/intel.h =================================================================== --- /dev/null +++ b/board/phycore_pxa270/intel.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ # # Submitted-By: Sascha Hauer, 2006-03-14 # Committed-By: Sascha Hauer # # Error: # # gcc4 fixes. copied from kernel source # # State: # # not sent upstream yet # Index: common/cmd_chggpio.c =================================================================== --- /dev/null +++ b/common/cmd_chggpio.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2004 + * Benedikt Spranger, b.spranger@pengutronix.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CFG_CMD_CHGGPIO + +#include +#include +#include + +int do_chggpio (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int gpio, af, lv; + + if ((argc != 2) && (argc != 5)) + { + printf ("usage:\t%s <0|1>\n\t%s \n", + argv [0], argv [0]); + return -1; + } + + gpio = simple_strtoul (argv[1], NULL, 0); + + if (gpio < 0 || gpio > 84) + { + printf ("unknown gpio %d\n", gpio); + return -1; + } + + if (argc == 2) + { + printf ("GPIO %02d: AF %1d %s %s\n", + gpio, (GAFR (gpio) >> (gpio%16)*2) & 0x3, + (GPDR (gpio) & GPIO_bit(gpio)) ? "OUT":"IN", + (GPLR (gpio) & GPIO_bit(gpio)) ? "high":"low"); + + return 0; + } + + af = simple_strtoul (argv[2], NULL, 0); + + if ((af < 0) || (af > 3)) + { + printf ("unknown alternate function #%d\n", af); + return 0; + } + + GAFR (gpio) &= ~(0x3 << (gpio%16)*2); + GAFR (gpio) |= af << (gpio%16)*2; + + lv = simple_strtoul (argv[4], NULL, 0); + + if (lv) + GPSR(gpio) |= GPIO_bit(gpio); + else + GPCR(gpio) |= GPIO_bit(gpio); + + if (!strncmp("in", argv [3], 2) || !strncmp("IN", argv [3], 2)) + GPDR(gpio) &= ~GPIO_bit(gpio); + else if (!strncmp("out", argv [3], 3) || !strncmp("OUT", argv [3], 3)) + GPDR(gpio) |= GPIO_bit(gpio); + else + printf ("%s must be \"in\" or \"out\"\n", argv [3]); + + return 0; +} + +U_BOOT_CMD( + chggpio, 5, 2, do_chggpio, + "chggpio - chg GPIO <0|1>\n", + "hilfe\n" +); + +#endif /* CFG_CMD_GPIOPXA */ Index: common/cmd_pxagpio.c =================================================================== --- /dev/null +++ b/common/cmd_pxagpio.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2004 + * Benedikt Spranger, b.spranger@pengutronix.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CFG_CMD_GPIOPXA + +#include +#include +#include +#include + +int do_pxagpio (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int i,j; + int gpio, af, dir; + + if (argc != 3) + { + printf ("usage: %s \n", argv [0]); + return -1; + } + + gpio = simple_strtoul (argv[1], NULL, 16); + + if (gpio < 0 || gpio > 84) + { + printf ("unknown gpio %d\n", gpio); + return -1; + } + + dir = GPDR(gpio); + + GPDR(gpio) |= GPIO_bit(gpio); + + for (i = 0; i < simple_strtoul (argv[2], NULL, 16); i++) + { + GPSR(gpio) |= GPIO_bit(gpio); + for(j=0;j<100;j++) + udelay(5000); + if(ctrlc()) { + printf("abort\n"); + return; + } + GPCR(gpio) |= GPIO_bit(gpio); + for(j=0;j<100;j++) + udelay(5000); + } + + GPDR(gpio) &= ~GPIO_bit(gpio); + + return 0; +} + +U_BOOT_CMD( + pxagpio, 3, 2, do_pxagpio, + "pxagpio - toggle GPIO times\n", + "hilfe\n" +); + +#endif /* CFG_CMD_GPIOPXA */