diff -Nru u-boot-1.1.6/board/mainstone/lowlevel_init.S u-boot-1.1.6-dest/board/mainstone/lowlevel_init.S --- u-boot-1.1.6/board/mainstone/lowlevel_init.S 2007-01-30 13:28:48.000000000 +0100 +++ u-boot-1.1.6-dest/board/mainstone/lowlevel_init.S 2007-01-18 13:33:06.000000000 +0100 @@ -45,7 +45,7 @@ /*********** Write out to HEX 7 segment leds *********/ -#define DEBUG_HEXLOG +/* #define DEBUG_HEXLOG */ #ifdef DEBUG_HEXLOG #define LEDCTL 0x08000040 @@ -106,93 +106,6 @@ .globl lowlevel_init lowlevel_init: - - /* Set up GPIO pins first */ - - ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL - str r1, [r0] - - ldr r0, =GPSR3 - ldr r1, =CFG_GPSR3_VAL - str r1, [r0] - - ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL - str r1, [r0] - - ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL - str r1, [r0] - - ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL - str r1, [r0] - - ldr r0, =GPCR3 - ldr r1, =CFG_GPCR3_VAL - str r1, [r0] - - ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL - str r1, [r0] - - ldr r0, =GPDR3 - ldr r1, =CFG_GPDR3_VAL - str r1, [r0] - - ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL - str r1, [r0] - - ldr r0, =GAFR3_L - ldr r1, =CFG_GAFR3_L_VAL - str r1, [r0] - - ldr r0, =GAFR3_U - ldr r1, =CFG_GAFR3_U_VAL - str r1, [r0] - - ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL - str r1, [r0] - /* ---------------------------------------------------------------- */ /* Enable memory interface */ /* */ @@ -386,7 +299,7 @@ /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ - /* 100..200 µsec. */ + /* 100..200 sec. */ /* The sequence below is based on the recommended init steps detailed */ /* in the Intel PXA255 Processor Developer's Manual Section 6.11 */ @@ -440,13 +353,100 @@ hexlog #0x6 /* HEXLOG */ -setvoltage: + /* Set up GPIO pins */ + + ldr r0, =GPSR0 + ldr r1, =CFG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CFG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CFG_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CFG_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CFG_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CFG_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CFG_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CFG_GPCR3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CFG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CFG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CFG_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CFG_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CFG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CFG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CFG_GAFR1_L_VAL + str r1, [r0] + ldr r0, =GAFR1_U + ldr r1, =CFG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CFG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CFG_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CFG_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CFG_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CFG_PSSR_VAL + str r1, [r0] + +#ifdef CFG_INITPXAVOLTAGE +setvoltage: mov r10, lr bl initPXAvoltage /* In case the board is rebooting with a */ mov lr, r10 /* low voltage raise it up to a good one. */ hexlog #0x7 /* HEXLOG */ +#endif wakeup: /* Are we waking from sleep? */ diff -Nru u-boot-1.1.6/cpu/pxa/start.S u-boot-1.1.6-dest/cpu/pxa/start.S --- u-boot-1.1.6/cpu/pxa/start.S 2007-01-30 13:28:48.000000000 +0100 +++ u-boot-1.1.6-dest/cpu/pxa/start.S 2007-01-17 18:18:42.000000000 +0100 @@ -263,11 +263,11 @@ /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will - * find a lowlevel_init.S in your board directory. + * find a lowlevel_init.S in your board directory. */ mov ip, lr bl lowlevel_init mov lr, ip - */ + /* */ /* Memory interfaces are working. Disable MMU and enable I-cache. */ /* mk: hmm, this is not in the monahans docs, leave it now but diff -Nru u-boot-1.1.6/include/configs/mainstone.h u-boot-1.1.6-dest/include/configs/mainstone.h --- u-boot-1.1.6/include/configs/mainstone.h 2007-01-30 13:28:48.000000000 +0100 +++ u-boot-1.1.6-dest/include/configs/mainstone.h 2007-01-18 11:31:47.000000000 +0100 @@ -144,7 +144,7 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM_PHYSICAL_BASE */ /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ @@ -164,37 +164,65 @@ * GPIO settings for Mainstone */ -#define CFG_GPSR0_VAL 0x00708800 -#define CFG_GPSR1_VAL 0x03cf0002 -#define CFG_GPSR2_VAL 0x0021FC00 -#define CFG_GPSR3_VAL 0x00000000 - -#define CFG_GPCR0_VAL 0x00001000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPCR3_VAL 0x00000000 - -#define CFG_GPDR0_VAL 0xC27B9C04 -#define CFG_GPDR1_VAL 0x00EFAA83 -#define CFG_GPDR2_VAL 0x0E23FC00 -#define CFG_GPDR3_VAL 0x001E1F81 +#define CFG_GPSR0_VAL 0x00709C04 /* GPSR0_value */ +#define CFG_GPSR1_VAL 0x00CF0002 /* GPSR1_value */ +#define CFG_GPSR2_VAL 0x052DE000 /* GPSR2_value */ +#define CFG_GPSR3_VAL 0x00160000 /* GPSR3_value */ + +#define CFG_GPCR0_VAL 0x00043000 /* GPCR0_value */ +#define CFG_GPCR1_VAL 0x00100380 /* GPCR1_value */ +#define CFG_GPCR2_VAL 0x08000000 /* GPCR1_value */ +#define CFG_GPCR3_VAL 0x00080003 /* GPCR1_value */ + +#define CFG_GPDR0_VAL 0xC991F800 /* GPDR0_value */ +#define CFG_GPDR1_VAL 0xFCFFAB83 /* GPDR1_value */ +#define CFG_GPDR2_VAL 0xF3FFFFF /* GPDR2_value */ +#define CFG_GPDR3_VAL 0x01E1F80 /* GPDR3_value */ -#define CFG_GAFR0_L_VAL 0x94F00000 +/*#define CFG_GAFR0_L_VAL 0x94F00000 #define CFG_GAFR0_U_VAL 0x015A859A #define CFG_GAFR1_L_VAL 0x999A955A #define CFG_GAFR1_U_VAL 0x0005A4AA #define CFG_GAFR2_L_VAL 0x6AA00000 #define CFG_GAFR2_U_VAL 0x55A8041A #define CFG_GAFR3_L_VAL 0x56AA955A -#define CFG_GAFR3_U_VAL 0x00000001 +#define CFG_GAFR3_U_VAL 0x00000001 */ + +#define CFG_GAFR0_L_VAL 0x3 << 22 | 0x2 << 30 +#define CFG_GAFR0_U_VAL 0x1 << 24 | 0x1 << 26 | 0x2 << 28 | 0x2 << 30 +#define CFG_GAFR1_L_VAL 0x2 << 0 | 0x2 << 2 | 0x1 << 4 | 0x1 << 6 | 0x1 << 8 | 0x1 << 10 | 0x1 << 12 | 0x2 << 14 | 0x2 << 16 | 0x2 << 18 | 0x1 << 20 | 0x2 << 22 | 0x1 << 24 | 0x2 << 26 | 0x2 << 28 | 0x1 << 30 +#define CFG_GAFR1_U_VAL 0x2 << 0 | 0x2 << 2 | 0x1 << 4 | 0x1 << 6 | 0x1 << 8 | 0x1 << 10 | 0x1 << 12 | 0x2 << 14 | 0x2 << 16 | 0x2 << 18 | 0x1 << 20 | 0x2 << 22 | 0x1 << 24 | 0x2 << 26 | 0x2 << 28 | 0x1 << 30 +#define CFG_GAFR2_L_VAL 0x2 << 0 | 0x2 << 2 | 0x2 << 4 | 0x2 << 6 | 0x2 << 12 | 0x2 << 14 | 0x1 << 16 | 0x1 << 18 +#define CFG_GAFR2_U_VAL 0x2 << 28 | 0x1 << 30 +#define CFG_GAFR3_L_VAL 0x1 << 0 | 0x1 << 2 | 0x3 << 4 | 0x3 << 6 | 0x1 << 8 | 0x1 << 10 | 0x1 << 12 | 0x2 << 14 | 0x2 << 16 | 0x2 << 18 | 0x2 << 20 | 0x2 << 22 | 0x2 << 24 | 0x1 << 26 | 0x1 << 28 | 0x1 << 30 +#define CFG_GAFR3_U_VAL 0x1 << 0 | 0x2 << 2 | 0x1 << 10 | 0x1 << 12 + +/* +xlli_GAFR0_L_value EQU (GPIO_11_AF3_48MCLK:OR:GPIO_15_AF2_nCS1) + 0x3 << 22 | 0x2 << 30 +xlli_GAFR0_U_value EQU (GPIO_18_AF1_RDY:OR:GPIO_28_AF1_AC97_I2S_BITCLK:OR:GPIO_29_AF1_AC97SDATAIN0:OR:GPIO_30_AF2_AC97SDATAOUT:OR:GPIO_31_AF2_AC97SYNC) + 0x1 << 24 | 0x1 << 26 | 0x2 << 28 | 0x2 << 30 +xlli_GAFR1_L_value EQU (GPIO_32_AF2_MMCLK:OR:GPIO_33_AF2_nCS5:OR:GPIO_34_AF1_FFRXD:OR:GPIO_35_AF1_FFCTS:OR:GPIO_36_AF1_FFDCD:OR:GPIO_37_AF1_FFDSR:OR:GPIO_38_AF1_FFRI:OR:GPIO_39_AF2_FFTXD:OR:GPIO_40_AF2_FFDTR:OR:GPIO_41_AF2_FFRTS:OR:GPIO_42_AF1_BTRXD:OR:GPIO_43_AF2_BTTXD:OR:GPIO_44_AF1_BTCTS:OR:GPIO_45_AF2_BTRTS:OR:GPIO_46_AF2_STDRXD_PWMOUT2:OR:GPIO_47_AF1_STDTXD) + 0x2 << 0 | 0x2 << 2 | 0x1 << 4 | 0x1 << 6 | 0x1 << 8 | 0x1 << 10 | 0x1 << 12 | 0x2 << 14 | 0x2 << 16 | 0x2 << 18 | 0x1 << 20 | 0x2 << 22 | 0x1 << 24 | 0x2 << 26 | 0x2 << 28 | 0x1 << 30 +xlli_GAFR1_U_value EQU (GPIO_48_AF2_PCMCIAnPOE:OR:GPIO_49_AF2_nPWE:OR:GPIO_50_AF2_PCMCIAnPIOR:OR:GPIO_51_AF2_PCMCIAnPIOW:OR:GPIO_54_AF2_BBOBWAIT_PCMCIAnPCE2:OR:GPIO_55_AF2_BBIBDAT1_PCMCIAnPREG:OR:GPIO_56_AF1_PCMCIAnPWAIT:OR:GPIO_57_AF1_PCMCIAnIOIS16) + 0x2 << 0 | 0x2 << 2 | 0x2 << 4 | 0x2 << 6 | 0x2 << 12 | 0x2 << 14 | 0x1 << 16 | 0x1 << 18 +xlli_GAFR2_L_value EQU (GPIO_78_AF2_nCS2:OR:GPIO_79_AF1_PCMCIAPSKTSEL) + 0x2 << 28 | 0x1 << 30 +xlli_GAFR2_U_value EQU (GPIO_80_AF2_MBREQ_nCS4:OR:GPIO_85_AF1_PCMCIAnPCE1:OR:GPIO_89_AF1_AC97SYSCLK:OR:GPIO_92_AF1_MMDAT0:OR:GPIO_93_AF1_KPDKIN0:OR:GPIO_94_AF1_KPDKIN1:OR:GPIO_95_AF1_KPDKIN2) + 0x2 << 0 | 0x1 << 10 | 0x1 << 18 | 0x1 << 24 | 0x1 << 26 | 0x1 << 28 | 0x1 << 30 +xlli_GAFR3_L_value EQU (GPIO_96_AF1_KPDKIN3:OR:GPIO_97_AF1_KPDKIN4:OR:GPIO_98_AF3_KPMKIN4:OR:GPIO_99_AF3_KPMKIN5:OR:GPIO_100_AF1_KPMKIN0:OR:GPIO_101_AF1_KPMKIN1:OR:GPIO_102_AF1_KPMKIN2:OR:GPIO_103_AF2_KPMKOUT0:OR:GPIO_104_AF2_KPMKOUT1:OR:GPIO_105_AF2_KPMKOUT2:OR:GPIO_106_AF2_KPMKOUT3:OR:GPIO_107_AF2_KPMKOUT4:OR:GPIO_108_AF2_KPMKOUT5:OR:GPIO_109_AF1_MMDAT1:OR:GPIO_110_AF1_MMDAT2:OR:GPIO_111_AF1_MMDAT3) + 0x1 << 0 | 0x1 << 2 | 0x3 << 4 | 0x3 << 6 | 0x1 << 8 | 0x1 << 10 | 0x1 << 12 | 0x2 << 14 | 0x2 << 16 | 0x2 << 18 | 0x2 << 20 | 0x2 << 22 | 0x2 << 24 | 0x1 << 26 | 0x1 << 28 | 0x1 << 30 +xlli_GAFR3_U_value EQU (GPIO_112_AF1_MMCMD:OR:GPIO_113_AF2_AC97nRESET:OR:GPIO_117_AF1_SCL:OR:GPIO_118_AF1_SDA) + 0x1 << 0 | 0x2 << 2 | 0x1 << 10 | 0x1 << 12 +*/ #define CFG_PSSR_VAL 0x20 // ??????????? /* * Clock settings */ -#define CFG_CKEN 0x00400200 -#define CFG_CCCR 0x02000290 /* 520Mhz */ +#define CFG_CKEN 0x00400200 /* CKEN_value */ +#define CFG_CCCR 0x00000107 /* CCCR_value */ /* 520Mhz */ /* #define CFG_CCCR 0x02000210 416 Mhz */ /* @@ -202,26 +230,26 @@ */ //#define CFG_MSC0_VAL 0x39F2A7A3 // DO NOT SET IT ! -#define CFG_MSC1_VAL 0x0000A691 -#define CFG_MSC2_VAL 0x0000B884 - -#define CFG_MDCNFG_VAL 0x00000AC8 /* start with SDRAM part. disabled */ -#define CFG_MDREFR_VAL 0x20ca2018 -#define CFG_MDMRS_VAL 0x00000000 - -#define CFG_FLYCNFG_VAL 0x00010001 -#define CFG_SXCNFG_VAL 0x40044004 +#define CFG_MSC1_VAL 0x7FF07FF4 /* MSC1_value */ +#define CFG_MSC2_VAL 0x7FFC7FF4 /* MSC2_value */ +#define CFG_MDCNFG_VAL 0x80000AD0 /* MDCNFG_value */ /* start with SDRAM part. disabled */ +#define CFG_MDREFR_VAL 0x0000001E /* MDREFR_value */ +#define CFG_MDMRS_VAL 0x00000000 /* MDMRS_value */ + +#define CFG_FLYCNFG_VAL 0x00010001 /* FLYCNFG_value */ +#define CFG_SXCNFG_VAL 0x40044004 /* SXCNFG_value */ +// /* * PCMCIA and CF Interfaces */ -#define CFG_MECR_VAL 0x00000001 -#define CFG_MCMEM0_VAL 0x00010204 -#define CFG_MCMEM1_VAL 0x00010204 -#define CFG_MCATT0_VAL 0x00010204 -#define CFG_MCATT1_VAL 0x00010204 -#define CFG_MCIO0_VAL 0x0000c108 -#define CFG_MCIO1_VAL 0x0001c108 +#define CFG_MECR_VAL 0x00000000 /* MECR_value */ +#define CFG_MCMEM0_VAL 0x0002470F /* MCMEM0_value */ +#define CFG_MCMEM1_VAL 0x0002470F /* MCMEM1_value */ +#define CFG_MCATT0_VAL 0x0002C80F /* MCATT0_value */ +#define CFG_MCATT1_VAL 0x0002C80F /* MCATT1_value */ +#define CFG_MCIO0_VAL 0x0002471F /* MCIO0_value */ +#define CFG_MCIO1_VAL 0x0002471F /* MCIO1_value */ //#define CONFIG_PXA_PCMCIA 1 //#define CONFIG_PXA_IDE 1 @@ -277,9 +305,9 @@ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* FPGA */ -#define MST_FPGA_BASE 0x08000000 -#define MST_LEDDAT1 0x08000010 +#define MST_FPGA_BASE 0x08000000 /* PLATFORM_REGISTERS */ +#define MST_LEDDAT1 0x08000010 /* PLATFORM_HEXLED_DATA_offset */ #define MST_LEDDAT2 0x08000014 -#define MST_LEDCTL 0x08000040 +#define MST_LEDCTL 0x08000040 /* PLATFORM_LED_CONTROL_offset */ #endif /* __CONFIG_H */ diff -Nru u-boot-1.1.6/MAKEALL u-boot-1.1.6-dest/MAKEALL --- u-boot-1.1.6/MAKEALL 2006-11-02 15:15:01.000000000 +0100 +++ u-boot-1.1.6-dest/MAKEALL 2007-01-17 00:16:03.000000000 +0100 @@ -218,9 +218,9 @@ LIST_pxa=" \ adsvix cerf250 cradle csb226 \ - delta innokom lubbock pleb2 \ - pxa255_idp wepep250 xaeniax xm250 \ - xsengine zylonite \ + delta innokom lubbock mainstone \ + pleb2 pxa255_idp wepep250 xaeniax \ + xm250 xsengine zylonite \ " LIST_ixp="ixdp425 ixdpg425 pdnb3"