875 lines
28 KiB
Diff
875 lines
28 KiB
Diff
--- dyngen-exec.h 24 Apr 2005 18:01:56 -0000 1.25
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+++ dyngen-exec.h 11 May 2005 20:38:33 -0000
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@@ -155,7 +155,12 @@ extern int printf(const char *, ...);
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#endif
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/* force GCC to generate only one epilog at the end of the function */
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+#if defined(__i386__) || defined(__x86_64__)
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+/* Also add 4 bytes of padding so that we can replace the ret with a jmp. */
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+#define FORCE_RET() asm volatile ("nop;nop;nop;nop");
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+#else
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#define FORCE_RET() asm volatile ("");
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+#endif
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#ifndef OPPROTO
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#define OPPROTO
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@@ -205,12 +210,19 @@ extern int __op_jmp0, __op_jmp1, __op_jm
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#endif
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#ifdef __i386__
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-#define EXIT_TB() asm volatile ("ret")
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-#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
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+/* Dyngen will replace hlt instructions with a ret instruction. Inserting a
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+ ret directly would confuse dyngen. */
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+#define EXIT_TB() asm volatile ("hlt")
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+/* Dyngen will replace cli with 0x9e (jmp).
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+ We generate the offset manually. */
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+#define GOTO_LABEL_PARAM(n) \
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+ asm volatile ("cli;.long " ASM_NAME(__op_gen_label) #n " - 1f;1:")
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#endif
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#ifdef __x86_64__
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-#define EXIT_TB() asm volatile ("ret")
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-#define GOTO_LABEL_PARAM(n) asm volatile ("jmp " ASM_NAME(__op_gen_label) #n)
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+/* The same as i386. */
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+#define EXIT_TB() asm volatile ("hlt")
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+#define GOTO_LABEL_PARAM(n) \
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+ asm volatile ("cli;.long " ASM_NAME(__op_gen_label) #n " - 1f;1:")
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#endif
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#ifdef __powerpc__
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#define EXIT_TB() asm volatile ("blr")
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--- dyngen.c 27 Apr 2005 19:55:58 -0000 1.40
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+++ dyngen.c 11 May 2005 20:38:33 -0000
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@@ -32,6 +32,8 @@
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#include "config-host.h"
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+//#define DEBUG_OP
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+
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/* NOTE: we test CONFIG_WIN32 instead of _WIN32 to enabled cross
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compilation */
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#if defined(CONFIG_WIN32)
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@@ -1343,6 +1345,639 @@ int arm_emit_ldr_info(const char *name,
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#endif
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+#if defined(HOST_I386) || defined(HOST_X86_64)
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+
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+/* This byte is the first byte of an instruction. */
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+#define FLAG_INSN (1 << 0)
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+/* This byte has been processed as part of an instruction. */
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+#define FLAG_SCANNED (1 << 1)
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+/* This instruction is a return instruction. Gcc cometimes generates prefix
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+ bytes, so may be more than one byte long. */
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+#define FLAG_RET (1 << 2)
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+/* This is either the target of a jump, or the preceeding instruction uses
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+ a pc-relative offset. */
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+#define FLAG_TARGET (1 << 3)
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+/* This is a magic instruction that needs fixing up. */
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+#define FLAG_EXIT (1 << 4)
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+#define MAX_EXITS 5
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+
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+static void
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+bad_opcode(const char *name, uint32_t op)
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+{
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+ error("Unsupported opcode %0*x in %s", (op > 0xff) ? 4 : 2, op, name);
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+}
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+
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+/* Mark len bytes as scanned, Returns insn_size + len. Reports an error
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+ if these bytes have already been scanned. */
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+static int
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+eat_bytes(const char *name, char *flags, int insn, int insn_size, int len)
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+{
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+ while (len > 0) {
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+ /* This should never occur in sane code. */
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+ if (flags[insn + insn_size] & FLAG_SCANNED)
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+ error ("Overlapping instructions in %s", name);
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+ flags[insn + insn_size] |= FLAG_SCANNED;
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+ insn_size++;
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+ len--;
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+ }
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+ return insn_size;
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+}
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+
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+static void
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+trace_i386_insn (const char *name, uint8_t *start_p, char *flags, int insn,
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+ int len)
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+{
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+ uint8_t *ptr;
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+ uint8_t op;
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+ int modrm;
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+ int is_prefix;
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+ int op_size;
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+ int addr_size;
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+ int insn_size;
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+ int is_ret;
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+ int is_condjmp;
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+ int is_jmp;
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+ int is_exit;
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+ int is_pcrel;
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+ int immed;
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+ int seen_rexw;
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+ int32_t disp;
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+
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+ ptr = start_p + insn;
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+ /* nonzero if this insn has a ModR/M byte. */
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+ modrm = 1;
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+ /* The size of the immediate value in this instruction. */
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+ immed = 0;
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+ /* The operand size. */
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+ op_size = 4;
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+ /* The address size */
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+ addr_size = 4;
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+ /* The total length of this instruction. */
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+ insn_size = 0;
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+ is_prefix = 1;
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+ is_ret = 0;
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+ is_condjmp = 0;
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+ is_jmp = 0;
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+ is_exit = 0;
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+ seen_rexw = 0;
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+ is_pcrel = 0;
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+
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+ while (is_prefix) {
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+ op = ptr[insn_size];
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+ insn_size = eat_bytes(name, flags, insn, insn_size, 1);
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+ is_prefix = 0;
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+ switch (op >> 4) {
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+ case 0:
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+ case 1:
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+ case 2:
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+ case 3:
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+ if (op == 0x0f) {
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+ /* two-byte opcode. */
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+ op = ptr[insn_size];
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+ insn_size = eat_bytes(name, flags, insn, insn_size, 1);
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+ switch (op >> 4) {
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+ case 0:
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+ if ((op & 0xf) > 3)
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+ modrm = 0;
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+ break;
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+ case 1: /* vector move or prefetch */
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+ case 2: /* various moves and vector compares. */
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+ case 4: /* cmov */
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+ case 5: /* vector instructions */
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+ case 6:
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+ case 13:
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+ case 14:
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+ case 15:
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+ break;
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+ case 7: /* mmx */
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+ if (op & 0x77) /* emms */
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+ modrm = 0;
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+ break;
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+ case 3: /* wrmsr, rdtsc, rdmsr, rdpmc, sysenter, sysexit */
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+ modrm = 0;
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+ break;
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+ case 8: /* long conditional jump */
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+ is_condjmp = 1;
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+ immed = op_size;
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+ modrm = 0;
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+ break;
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+ case 9: /* setcc */
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+ break;
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+ case 10:
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+ switch (op & 0x7) {
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+ case 0: /* push fs/gs */
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+ case 1: /* pop fs/gs */
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+ case 2: /* cpuid/rsm */
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+ modrm = 0;
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+ break;
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+ case 4: /* shld/shrd immediate */
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+ immed = 1;
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+ break;
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+ default: /* Normal instructions with a ModR/M byte. */
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+ break;
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+ }
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+ break;
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+ case 11:
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+ switch (op & 0xf) {
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+ case 10: /* bt, bts, btr, btc */
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+ immed = 1;
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+ break;
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+ default:
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+ /* cmpxchg, lss, btr, lfs, lgs, movzx, btc, bsf, bsr
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+ undefined, and movsx */
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+ break;
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+ }
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+ break;
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+ case 12:
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+ if (op & 8) {
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+ /* bswap */
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+ modrm = 0;
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+ } else {
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+ switch (op & 0x7) {
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+ case 2:
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+ case 4:
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+ case 5:
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+ case 6:
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+ immed = 1;
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+ break;
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+ }
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+ } else if ((op & 0x07) <= 0x3) {
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+ /* General arithmentic ax. */
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+ } else if ((op & 0x07) <= 0x5) {
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+ /* General arithmetic ax, immediate. */
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+ if (op & 0x01)
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+ immed = op_size;
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+ else
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+ immed = 1;
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+ modrm = 0;
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+ } else if ((op & 0x23) == 0x22) {
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+ /* Segment prefix. */
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+ is_prefix = 1;
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+ } else {
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+ /* Segment register push/pop or DAA/AAA/DAS/AAS. */
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+ modrm = 0;
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+ }
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+ break;
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+
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+#if defined(HOST_X86_64)
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+ case 4: /* rex prefix. */
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+ is_prefix = 1;
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+ /* The address/operand size is actually 64-bit, but the immediate
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+ values in the instruction are still 32-bit. */
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+ op_size = 4;
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+ addr_size = 4;
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+ if (op & 8)
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+ seen_rexw = 1;
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+ break;
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+#else
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+ case 4: /* inc/dec register. */
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+#endif
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+ case 5: /* push/pop general register. */
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+ modrm = 0;
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+ break;
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+
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+ case 6:
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+ switch (op & 0x0f) {
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+ case 0: /* pusha */
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+ case 1: /* popa */
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+ modrm = 0;
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+ break;
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+ case 2: /* bound */
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+ case 3: /* arpl */
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+ break;
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+ case 4: /* FS */
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+ case 5: /* GS */
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+ is_prefix = 1;
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+ break;
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+ case 6: /* opcode size prefix. */
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+ op_size = 2;
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+ is_prefix = 1;
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+ break;
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+ case 7: /* Address size prefix. */
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+ addr_size = 2;
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+ is_prefix = 1;
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+ break;
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+ case 8: /* push immediate */
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+ case 10: /* pop immediate */
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+ immed = op_size;
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+ modrm = 0;
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+ break;
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+ case 9: /* imul immediate */
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+ case 11: /* imul immediate */
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+ immed = op_size;
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+ break;
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+ case 12: /* insb */
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+ case 13: /* insw */
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+ case 14: /* outsb */
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+ case 15: /* outsw */
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+ modrm = 0;
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+ break;
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+ }
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+ break;
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+
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+ case 7: /* Short conditional jump. */
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+ is_condjmp = 1;
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+ immed = 1;
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+ modrm = 0;
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+ break;
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+
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+ case 8:
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+ if ((op & 0xf) <= 3) {
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+ /* arithmetic immediate. */
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+ if ((op & 3) == 1)
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+ immed = op_size;
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+ else
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+ immed = 1;
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+ }
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+ /* else test, xchg, mov, lea or pop general. */
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+ break;
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+
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+ case 9:
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+ /* Various single-byte opcodes with no modrm byte. */
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+ modrm = 0;
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+ if (op == 10) {
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+ /* Call */
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+ immed = 4;
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+ }
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+ break;
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+
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+ case 10:
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+ switch ((op & 0xe) >> 1) {
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+ case 0: /* mov absoliute immediate. */
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+ case 1:
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+ if (seen_rexw)
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+ immed = 8;
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+ else
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+ immed = addr_size;
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+ break;
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+ case 4: /* test immediate. */
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+ if (op & 1)
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+ immed = op_size;
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+ else
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+ immed = 1;
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+ break;
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+ default: /* Various string ops. */
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+ break;
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+ }
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+ modrm = 0;
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+ break;
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+
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+ case 11: /* move immediate to register */
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+ if (op & 8) {
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+ if (seen_rexw)
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+ immed = 8;
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+ else
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+ immed = op_size;
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+ } else {
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+ immed = 1;
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+ }
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+ modrm = 0;
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+ break;
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+
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+ case 12:
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+ switch (op & 0xf) {
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+ case 0: /* shift immediate */
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+ case 1:
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+ immed = 1;
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+ break;
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+ case 2: /* ret immediate */
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+ immed = 2;
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+ modrm = 0;
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+ bad_opcode(name, op);
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+ break;
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+ case 3: /* ret */
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+ modrm = 0;
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+ is_ret = 1;
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+ case 4: /* les */
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+ case 5: /* lds */
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+ break;
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+ case 6: /* mov immediate byte */
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+ immed = 1;
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+ break;
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+ case 7: /* mov immediate */
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+ immed = op_size;
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+ break;
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+ case 8: /* enter */
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+ /* TODO: Is this right? */
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+ immed = 3;
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+ modrm = 0;
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+ break;
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+ case 10: /* retf immediate */
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+ immed = 2;
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+ modrm = 0;
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+ bad_opcode(name, op);
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+ break;
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+ case 13: /* int */
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+ immed = 1;
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+ modrm = 0;
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+ break;
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+ case 11: /* retf */
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+ case 15: /* iret */
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+ modrm = 0;
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+ bad_opcode(name, op);
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+ break;
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+ default: /* leave, int3 or into */
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+ modrm = 0;
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+ break;
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+ }
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+ break;
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+
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+ case 13:
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+ if ((op & 0xf) >= 8) {
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+ /* Coprocessor escape. For our purposes this is just a normal
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+ instruction with a ModR/M byte. */
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+ } else if ((op & 0xf) >= 4) {
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+ /* AAM, AAD or XLAT */
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+ modrm = 0;
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+ }
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+ /* else shift instruction */
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+ break;
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+
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+ case 14:
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+ switch ((op & 0xc) >> 2) {
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+ case 0: /* loop or jcxz */
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+ is_condjmp = 1;
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+ immed = 1;
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+ break;
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+ case 1: /* in/out immed */
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+ immed = 1;
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+ break;
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+ case 2: /* call or jmp */
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+ switch (op & 3) {
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+ case 0: /* call */
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+ immed = op_size;
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+ break;
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+ case 1: /* long jump */
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+ immed = 4;
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+ is_jmp = 1;
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+ break;
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+ case 2: /* far jmp */
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+ bad_opcode(name, op);
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+ break;
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+ case 3: /* short jmp */
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+ immed = 1;
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+ is_jmp = 1;
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+ break;
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+ }
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+ break;
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+ case 3: /* in/out register */
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+ break;
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+ }
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+ modrm = 0;
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+ break;
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+
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+ case 15:
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+ switch ((op & 0xe) >> 1) {
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+ case 0:
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+ case 1:
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+ is_prefix = 1;
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+ break;
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+ case 2:
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+ case 4:
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+ case 5:
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+ case 6:
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+ modrm = 0;
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+ /* Some privileged insns are used as markers. */
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+ switch (op) {
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+ case 0xf4: /* hlt: Exit translation block. */
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+ is_exit = 1;
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+ break;
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+ case 0xfa: /* cli: Jump to label. */
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+ is_exit = 1;
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+ immed = 4;
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+ break;
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+ case 0xfb: /* sti: TB patch jump. */
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+ /* Mark the insn for patching, but continue sscanning. */
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+ flags[insn] |= FLAG_EXIT;
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+ immed = 4;
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+ break;
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+ }
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+ break;
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+ case 3: /* unary grp3 */
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+ if ((ptr[insn_size] & 0x38) == 0) {
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+ if (op == 0xf7)
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+ immed = op_size;
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+ else
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+ immed = 1; /* test immediate */
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+ }
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+ break;
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+ case 7: /* inc/dec grp4/5 */
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+ /* TODO: This includes indirect jumps. We should fail if we
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+ encounter one of these. */
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+ break;
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+ }
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+ break;
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+ }
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+ }
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+
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+ if (modrm) {
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+ if (addr_size != 4)
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+ error("16-bit addressing mode used in %s", name);
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+
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+ disp = 0;
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+ modrm = ptr[insn_size];
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+ insn_size = eat_bytes(name, flags, insn, insn_size, 1);
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+ modrm &= 0xc7;
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+ switch ((modrm & 0xc0) >> 6) {
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+ case 0:
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+ if (modrm == 5)
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+ disp = 4;
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+ break;
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+ case 1:
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+ disp = 1;
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+ break;
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+ case 2:
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+ disp = 4;
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+ break;
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+ }
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+ if ((modrm & 0xc0) != 0xc0 && (modrm & 0x7) == 4) {
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+ /* SIB byte */
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+ if (modrm == 4 && (ptr[insn_size] & 0x7) == 5) {
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+ disp = 4;
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+ is_pcrel = 1;
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+ }
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+ insn_size = eat_bytes(name, flags, insn, insn_size, 1);
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+ }
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+ insn_size = eat_bytes(name, flags, insn, insn_size, disp);
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+ }
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+ insn_size = eat_bytes(name, flags, insn, insn_size, immed);
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+ if (is_condjmp || is_jmp) {
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+ if (immed == 1) {
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+ disp = (int8_t)*(ptr + insn_size - 1);
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+ } else {
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+ disp = (((int32_t)*(ptr + insn_size - 1)) << 24)
|
|
+ | (((int32_t)*(ptr + insn_size - 2)) << 16)
|
|
+ | (((int32_t)*(ptr + insn_size - 3)) << 8)
|
|
+ | *(ptr + insn_size - 4);
|
|
+ }
|
|
+ disp += insn_size;
|
|
+ /* Jumps to external symbols point to the address of the offset
|
|
+ before relocation. */
|
|
+ /* ??? These are probably a tailcall. We could fix them up by
|
|
+ replacing them with jmp to EOB + call, but it's easier to just
|
|
+ prevent the compiler generating them. */
|
|
+ if (disp == 1)
|
|
+ error("Unconditional jump (sibcall?) in %s", name);
|
|
+ disp += insn;
|
|
+ if (disp < 0 || disp > len)
|
|
+ error("Jump outside instruction in %s", name);
|
|
+
|
|
+ if ((flags[disp] & (FLAG_INSN | FLAG_SCANNED)) == FLAG_SCANNED)
|
|
+ error("Overlapping instructions in %s", name);
|
|
+
|
|
+ flags[disp] |= (FLAG_INSN | FLAG_TARGET);
|
|
+ is_pcrel = 1;
|
|
+ }
|
|
+ if (is_pcrel) {
|
|
+ /* Mark the following insn as a jump target. This will stop
|
|
+ this instruction being moved. */
|
|
+ flags[insn + insn_size] |= FLAG_TARGET;
|
|
+ }
|
|
+ if (is_ret)
|
|
+ flags[insn] |= FLAG_RET;
|
|
+
|
|
+ if (is_exit)
|
|
+ flags[insn] |= FLAG_EXIT;
|
|
+
|
|
+ if (!(is_jmp || is_ret || is_exit))
|
|
+ flags[insn + insn_size] |= FLAG_INSN;
|
|
+}
|
|
+
|
|
+/* Scan a function body. Returns the position of the return sequence.
|
|
+ Sets *patch_bytes to the number of bytes that need to be copied from that
|
|
+ location. If no patching is required (ie. the return is the last insn)
|
|
+ *patch_bytes will be set to -1. *plen is the number of code bytes to copy.
|
|
+ */
|
|
+static int trace_i386_op(const char * name, uint8_t *start_p, int *plen,
|
|
+ int *patch_bytes, int *exit_addrs)
|
|
+{
|
|
+ char *flags;
|
|
+ int more;
|
|
+ int insn;
|
|
+ int retpos;
|
|
+ int bytes;
|
|
+ int num_exits;
|
|
+ int len;
|
|
+ int last_insn;
|
|
+
|
|
+ len = *plen;
|
|
+ flags = malloc(len + 1);
|
|
+ memset(flags, 0, len + 1);
|
|
+ flags[0] |= FLAG_INSN;
|
|
+ more = 1;
|
|
+ while (more) {
|
|
+ more = 0;
|
|
+ for (insn = 0; insn < len; insn++) {
|
|
+ if ((flags[insn] & (FLAG_INSN | FLAG_SCANNED)) == FLAG_INSN) {
|
|
+ trace_i386_insn(name, start_p, flags, insn, len);
|
|
+ more = 1;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* Strip any unused code at the end of the function. */
|
|
+ while (len > 0 && flags[len - 1] == 0)
|
|
+ len--;
|
|
+
|
|
+ retpos = -1;
|
|
+ num_exits = 0;
|
|
+ last_insn = 0;
|
|
+ for (insn = 0; insn < len; insn++) {
|
|
+ if (flags[insn] & FLAG_RET) {
|
|
+ /* ??? In theory it should be possible to handle multiple return
|
|
+ points. In practice it's not worth the effort. */
|
|
+ if (retpos != -1)
|
|
+ error("Multiple return instructions in %s", name);
|
|
+ retpos = insn;
|
|
+ }
|
|
+ if (flags[insn] & FLAG_EXIT) {
|
|
+ if (num_exits == MAX_EXITS)
|
|
+ error("Too many block exits in %s", name);
|
|
+ exit_addrs[num_exits] = insn;
|
|
+ num_exits++;
|
|
+ }
|
|
+ if (flags[insn] & FLAG_INSN)
|
|
+ last_insn = insn;
|
|
+ }
|
|
+
|
|
+ exit_addrs[num_exits] = -1;
|
|
+ if (retpos == -1) {
|
|
+ if (num_exits == 0) {
|
|
+ error ("No return instruction found in %s", name);
|
|
+ } else {
|
|
+ retpos = len;
|
|
+ last_insn = len;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* If the return instruction is the last instruction we can just
|
|
+ remove it. */
|
|
+ if (retpos == last_insn)
|
|
+ *patch_bytes = -1;
|
|
+ else
|
|
+ *patch_bytes = 0;
|
|
+
|
|
+ /* Back up over any nop instructions. */
|
|
+ while (retpos > 0
|
|
+ && (flags[retpos] & FLAG_TARGET) == 0
|
|
+ && (flags[retpos - 1] & FLAG_INSN) != 0
|
|
+ && start_p[retpos - 1] == 0x90) {
|
|
+ retpos--;
|
|
+ }
|
|
+
|
|
+ if (*patch_bytes == -1) {
|
|
+ *plen = retpos;
|
|
+ free (flags);
|
|
+ return retpos;
|
|
+ }
|
|
+ *plen = len;
|
|
+
|
|
+ /* The ret is in the middle of the function. Find four more bytes that
|
|
+ so the ret can be replaced by a jmp. */
|
|
+ /* ??? Use a short jump where possible. */
|
|
+ bytes = 4;
|
|
+ insn = retpos + 1;
|
|
+ /* We can clobber everything up to the next jump target. */
|
|
+ while (insn < len && bytes > 0 && (flags[insn] & FLAG_TARGET) == 0) {
|
|
+ insn++;
|
|
+ bytes--;
|
|
+ }
|
|
+ if (bytes > 0) {
|
|
+ /* ???: Strip out nop blocks. */
|
|
+ /* We can't do the replacement without clobbering anything important.
|
|
+ Copy preceeding instructions(s) to give us some space. */
|
|
+ while (retpos > 0) {
|
|
+ /* If this byte is the target of a jmp we can't move it. */
|
|
+ if (flags[retpos] & FLAG_TARGET)
|
|
+ break;
|
|
+
|
|
+ (*patch_bytes)++;
|
|
+ bytes--;
|
|
+ retpos--;
|
|
+
|
|
+ /* Break out of the loop if we have enough space and this is either
|
|
+ the first byte of an instruction or a pad byte. */
|
|
+ if ((flags[retpos] & (FLAG_INSN | FLAG_SCANNED)) != FLAG_SCANNED
|
|
+ && bytes <= 0) {
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (bytes > 0)
|
|
+ error("Unable to replace ret with jmp in %s\n", name);
|
|
+
|
|
+ free(flags);
|
|
+ return retpos;
|
|
+}
|
|
+
|
|
+#endif
|
|
+
|
|
#define MAX_ARGS 3
|
|
|
|
/* generate op code */
|
|
@@ -1356,6 +1991,11 @@ void gen_code(const char *name, host_ulo
|
|
uint8_t args_present[MAX_ARGS];
|
|
const char *sym_name, *p;
|
|
EXE_RELOC *rel;
|
|
+#if defined(HOST_I386) || defined(HOST_X86_64)
|
|
+ int patch_bytes;
|
|
+ int retpos;
|
|
+ int exit_addrs[MAX_EXITS];
|
|
+#endif
|
|
|
|
/* Compute exact size excluding prologue and epilogue instructions.
|
|
* Increment start_offset to skip epilogue instructions, then compute
|
|
@@ -1366,33 +2006,12 @@ void gen_code(const char *name, host_ulo
|
|
p_end = p_start + size;
|
|
start_offset = offset;
|
|
#if defined(HOST_I386) || defined(HOST_X86_64)
|
|
-#ifdef CONFIG_FORMAT_COFF
|
|
- {
|
|
- uint8_t *p;
|
|
- p = p_end - 1;
|
|
- if (p == p_start)
|
|
- error("empty code for %s", name);
|
|
- while (*p != 0xc3) {
|
|
- p--;
|
|
- if (p <= p_start)
|
|
- error("ret or jmp expected at the end of %s", name);
|
|
- }
|
|
- copy_size = p - p_start;
|
|
- }
|
|
-#else
|
|
{
|
|
int len;
|
|
len = p_end - p_start;
|
|
- if (len == 0)
|
|
- error("empty code for %s", name);
|
|
- if (p_end[-1] == 0xc3) {
|
|
- len--;
|
|
- } else {
|
|
- error("ret or jmp expected at the end of %s", name);
|
|
- }
|
|
+ retpos = trace_i386_op(name, p_start, &len, &patch_bytes, exit_addrs);
|
|
copy_size = len;
|
|
}
|
|
-#endif
|
|
#elif defined(HOST_PPC)
|
|
{
|
|
uint8_t *p;
|
|
@@ -1559,6 +2178,13 @@ void gen_code(const char *name, host_ulo
|
|
}
|
|
|
|
if (gen_switch == 2) {
|
|
+#if defined(HOST_I386) || defined(HOST_X86_64)
|
|
+ if (patch_bytes != -1)
|
|
+ copy_size += patch_bytes;
|
|
+#ifdef DEBUG_OP
|
|
+ copy_size += 2;
|
|
+#endif
|
|
+#endif
|
|
fprintf(outfile, "DEF(%s, %d, %d)\n", name + 3, nb_args, copy_size);
|
|
} else if (gen_switch == 1) {
|
|
|
|
@@ -1761,7 +2387,43 @@ void gen_code(const char *name, host_ulo
|
|
#error unsupport object format
|
|
#endif
|
|
}
|
|
+ }
|
|
+ /* Replace the marker instructions with the actual opcodes. */
|
|
+ for (i = 0; exit_addrs[i] != -1; i++) {
|
|
+ int op;
|
|
+ switch (p_start[exit_addrs[i]])
|
|
+ {
|
|
+ case 0xf4: op = 0xc3; break; /* hlt -> ret */
|
|
+ case 0xfa: op = 0xe9; break; /* cli -> jmp */
|
|
+ case 0xfb: op = 0xe9; break; /* sti -> jmp */
|
|
+ default: error("Internal error");
|
|
+ }
|
|
+ fprintf(outfile,
|
|
+ " *(uint8_t *)(gen_code_ptr + %d) = 0x%x;\n",
|
|
+ exit_addrs[i], op);
|
|
+ }
|
|
+ /* Fix up the return instruction. */
|
|
+ if (patch_bytes != -1) {
|
|
+ if (patch_bytes) {
|
|
+ fprintf(outfile, " memcpy(gen_code_ptr + %d,"
|
|
+ "gen_code_ptr + %d, %d);\n",
|
|
+ copy_size, retpos, patch_bytes);
|
|
+ }
|
|
+ fprintf(outfile,
|
|
+ " *(uint8_t *)(gen_code_ptr + %d) = 0xe9;\n",
|
|
+ retpos);
|
|
+ fprintf(outfile,
|
|
+ " *(uint32_t *)(gen_code_ptr + %d) = 0x%x;\n",
|
|
+ retpos + 1, copy_size - (retpos + 5));
|
|
+
|
|
+ copy_size += patch_bytes;
|
|
}
|
|
+#ifdef DEBUG_OP
|
|
+ fprintf(outfile,
|
|
+ " *(uint16_t *)(gen_code_ptr + %d) = 0x9090;\n",
|
|
+ copy_size);
|
|
+ copy_size += 2;
|
|
+#endif
|
|
}
|
|
#elif defined(HOST_X86_64)
|
|
{
|
|
@@ -1793,6 +2455,42 @@ void gen_code(const char *name, host_ulo
|
|
}
|
|
}
|
|
}
|
|
+ /* Replace the marker instructions with the actual opcodes. */
|
|
+ for (i = 0; exit_addrs[i] != -1; i++) {
|
|
+ int op;
|
|
+ switch (p_start[exit_addrs[i]])
|
|
+ {
|
|
+ case 0xf4: op = 0xc3; break; /* hlt -> ret */
|
|
+ case 0xfa: op = 0xe9; break; /* cli -> jmp */
|
|
+ case 0xfb: op = 0xe9; break; /* sti -> jmp */
|
|
+ default: error("Internal error");
|
|
+ }
|
|
+ fprintf(outfile,
|
|
+ " *(uint8_t *)(gen_code_ptr + %d) = 0x%x;\n",
|
|
+ exit_addrs[i], op);
|
|
+ }
|
|
+ /* Fix up the return instruction. */
|
|
+ if (patch_bytes != -1) {
|
|
+ if (patch_bytes) {
|
|
+ fprintf(outfile, " memcpy(gen_code_ptr + %d,"
|
|
+ "gen_code_ptr + %d, %d);\n",
|
|
+ copy_size, retpos, patch_bytes);
|
|
+ }
|
|
+ fprintf(outfile,
|
|
+ " *(uint8_t *)(gen_code_ptr + %d) = 0xe9;\n",
|
|
+ retpos);
|
|
+ fprintf(outfile,
|
|
+ " *(uint32_t *)(gen_code_ptr + %d) = 0x%x;\n",
|
|
+ retpos + 1, copy_size - (retpos + 5));
|
|
+
|
|
+ copy_size += patch_bytes;
|
|
+ }
|
|
+#ifdef DEBUG_OP
|
|
+ fprintf(outfile,
|
|
+ " *(uint16_t *)(gen_code_ptr + %d) = 0x9090;\n",
|
|
+ copy_size);
|
|
+ copy_size += 2;
|
|
+#endif
|
|
}
|
|
#elif defined(HOST_PPC)
|
|
{
|
|
|
|
--- target-ppc/exec.h 13 Mar 2005 17:01:22 -0000 1.10
|
|
+++ target-ppc/exec.h 11 May 2005 20:38:35 -0000
|
|
@@ -33,11 +33,7 @@ register uint32_t T2 asm(AREG3);
|
|
#define FT1 (env->ft1)
|
|
#define FT2 (env->ft2)
|
|
|
|
-#if defined (DEBUG_OP)
|
|
-#define RETURN() __asm__ __volatile__("nop");
|
|
-#else
|
|
-#define RETURN() __asm__ __volatile__("");
|
|
-#endif
|
|
+#define RETURN() FORCE_RET()
|
|
|
|
#include "cpu.h"
|
|
#include "exec-all.h"
|
|
--- exec-all.h.orig 2005-09-04 19:11:31.000000000 +0200
|
|
+++ exec-all.h 2005-09-11 01:10:01.525044400 +0200
|
|
@@ -338,14 +338,15 @@
|
|
|
|
#elif defined(__i386__) && defined(USE_DIRECT_JUMP)
|
|
|
|
-/* we patch the jump instruction directly */
|
|
+/* we patch the jump instruction directly. Use sti in place of the actual
|
|
+ jmp instruction so that dyngen can patch in the correct result. */
|
|
#define GOTO_TB(opname, tbparam, n)\
|
|
do {\
|
|
asm volatile (".section .data\n"\
|
|
ASM_OP_LABEL_NAME(n, opname) ":\n"\
|
|
".long 1f\n"\
|
|
ASM_PREVIOUS_SECTION \
|
|
- "jmp " ASM_NAME(__op_jmp) #n "\n"\
|
|
+ "sti;.long " ASM_NAME(__op_jmp) #n " - 1f\n"\
|
|
"1:\n");\
|
|
} while (0)
|
|
|