From 7d1ff3a9ab4ab98c353c36f1c6853fb7b715699d Mon Sep 17 00:00:00 2001 From: Silvan Calarco Date: Sat, 6 Jan 2024 08:15:27 +0100 Subject: [PATCH] configured with --enable-stlink and --enable-rlink [release 0.7.0-2mamba;Fri Aug 16 2013] --- README.md | 2 + openocd-board-guruplug.cfg | 125 +++++++++++++++++++++++++++++++++ openocd-interface-guruplug.cfg | 14 ++++ openocd.spec | 99 ++++++++++++++++++++++++++ 4 files changed, 240 insertions(+) create mode 100644 openocd-board-guruplug.cfg create mode 100644 openocd-interface-guruplug.cfg create mode 100644 openocd.spec diff --git a/README.md b/README.md index fe3e92e..8e3c932 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,4 @@ # openocd +The "Open On-Chip Debugger" provides JTAG/SWD access from GDB (or directly with TCL scripts) to processors with ARM and MIPS based cores. + diff --git a/openocd-board-guruplug.cfg b/openocd-board-guruplug.cfg new file mode 100644 index 0000000..d7a8507 --- /dev/null +++ b/openocd-board-guruplug.cfg @@ -0,0 +1,125 @@ +# Marvell SheevaPlug + +source [find interface/guruplug.cfg] +source [find target/feroceon.cfg] + +$_TARGETNAME configure \ + -work-area-phys 0x10000000 \ + -work-area-size 65536 \ + -work-area-backup 0 + +arm7_9 dcc_downloads enable + +# this assumes the hardware default peripherals location before u-Boot moves it +nand device orion 0 0xd8000000 + +proc guruplug_init { } { + + # We need to assert DBGRQ while holding nSRST down. + # However DBGACK will be set only when nSRST is released. + jtag_reset 0 1 + feroceon.cpu arp_examine + halt 0 + jtag_reset 0 0 + wait_halt + + arm926ejs cp15 0 0 1 0 0x00052078 + + mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register + mww 0xD0001404 0x39543000 # Dunit Control Low Register + mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register + mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register + mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register + mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register + mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register + mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register + mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register + mww 0xD0001424 0x0000F17F # Dunit Control High Register + mww 0xD0001428 0x00085520 # Dunit Control High Register + mww 0xD000147c 0x00008552 # Dunit Control High Register + mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register + mww 0xD0001508 0x10000000 # CS1n Base Register + mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register + mww 0xD0001514 0x00000000 # CS2n Size Register + mww 0xD000151C 0x00000000 # CS3n Size Register + mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register + mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister + mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register + mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register + mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + mww 0xD0020204 0x00000000 # " + + mww 0xD0010000 0x01111111 # MPP 0 to 7 + mww 0xD0010004 0x11113322 # MPP 8 to 15 + mww 0xD0010008 0x00001111 # MPP 16 to 23 + + mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister + mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register + mww 0xD0010470 0x01C7D943 # NAND Flash Control Register + +} + +proc guruplug_reflash_uboot { } { + + # reflash the u-Boot binary and reboot into it + guruplug_init + nand probe 0 + nand erase 0 0 2 + nand write 0 openocd/uboot.bin 0 oob_softecc + resume + +} + +proc guruplug_reflash_uboot_env { } { + # reflash the u-boot environment variables area + guruplug_init + nand probe 0 + nand erase 0 2 4 + nand write 0 openocd/uboot-env.bin 0x00040000 oob_softecc + resume +} + +proc guruplug_load_uboot { } { + + # load u-Boot into RAM and execute it + guruplug_init + load_image uboot.elf + verify_image uboot.elf + resume 0x00600000 + +} diff --git a/openocd-interface-guruplug.cfg b/openocd-interface-guruplug.cfg new file mode 100644 index 0000000..e67a49d --- /dev/null +++ b/openocd-interface-guruplug.cfg @@ -0,0 +1,14 @@ +# +# Marvel SheevaPlug Development Kit +# +# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp +# + +interface ft2232 +ft2232_layout sheevaplug +ft2232_vid_pid 0x9e88 0x9e8f +ft2232_device_desc "SheevaPlug JTAGKey FT2232D B" +#ft2232_vid_pid 0x0403 0x6010 +#ft2232_device_desc "Dual RS232" +jtag_khz 2000 + diff --git a/openocd.spec b/openocd.spec new file mode 100644 index 0000000..a637775 --- /dev/null +++ b/openocd.spec @@ -0,0 +1,99 @@ +Name: openocd +Version: 0.7.0 +Release: 2mamba +Summary: Free and Open On-Chip Debugging, In-System Programming and Boundary-Scan Testing +Group: System/Kernel and Hardware +Vendor: openmamba +Distribution: openmamba +Packager: Silvan Calarco +URL: http://openocd.sourceforge.net/ +Source: http://downloads.sourceforge.net/project/openocd/openocd/%{version}/openocd-%{version}.tar.bz2 +Source1: openocd-board-guruplug.cfg +Source2: openocd-interface-guruplug.cfg +License: GPL +## AUTOBUILDREQ-BEGIN +BuildRequires: glibc-devel +BuildRequires: libftdi-devel +BuildRequires: libpcre-devel +BuildRequires: libselinux-devel +BuildRequires: libsepol-devel +BuildRequires: libusb-compat-devel +BuildRequires: libusbx-devel +BuildRequires: udev-devel +## AUTOBUILDREQ-END +Requires(post): %{__install_info} +Requires(preun): %{__install_info} +BuildRoot: %{_tmppath}/%{name}-%{version}-root + +%description +The "Open On-Chip Debugger" provides JTAG/SWD access from GDB (or directly with TCL scripts) to processors with ARM and MIPS based cores. + +%debug_package + +%prep +%setup -q + +%build +%configure \ + --enable-ft2232_libftdi \ + --enable-libusb0 \ + --enable-stlink \ + --enable-rlink + +%make + +%install +[ "%{buildroot}" != / ] && rm -rf "%{buildroot}" +%makeinstall + +install -m0644 %{SOURCE1} %{buildroot}%{_datadir}/openocd/scripts/board/guruplug.cfg +install -m0644 %{SOURCE2} %{buildroot}%{_datadir}/openocd/scripts/interface/guruplug.cfg + +install -d -m0755 %{buildroot}/lib/udev/rules.d +mv %{buildroot}%{_datadir}/openocd/contrib/openocd.udev %{buildroot}/lib/udev/rules.d/90-openocd.rules + +%clean +[ "%{buildroot}" != / ] && rm -rf "%{buildroot}" + +%post +%install_info %{name}.info +%install_info %{name}.info-1 +%install_info %{name}.info-2 +exit 0 + +%preun +%uninstall_info %{name}.info +%uninstall_info %{name}.info-1 +%uninstall_info %{name}.info-2 +exit 0 + +%files +%defattr(-,root,root) +%{_bindir}/openocd +%{_libdir}/libopenocd.a +%{_libdir}/libopenocd.la +/lib/udev/rules.d/90-openocd.rules +%{_infodir}/openocd.info-1.gz +%{_infodir}/openocd.info-2.gz +%{_infodir}/openocd.info.gz +%{_mandir}/man1/openocd.1.gz +%dir %{_datadir}/openocd +%dir %{_datadir}/openocd/contrib +%{_datadir}/openocd/contrib/* +%dir %{_datadir}/openocd/scripts +%{_datadir}/openocd/scripts/* +%doc AUTHORS COPYING + +%changelog +* Fri Aug 16 2013 Silvan Calarco 0.7.0-2mamba +- configured with --enable-stlink and --enable-rlink + +* Sun May 05 2013 Automatic Build System 0.7.0-1mamba +- automatic version update by autodist + +* Wed Dec 19 2012 Silvan Calarco 0.6.1-2mamba +- provide guruplug server scripts from http://www.plugcomputer.org/405/us/guru-plug/docs/Guruplug-installer.tar.gz +- install udev rules file in proper directory + +* Wed Dec 19 2012 Silvan Calarco 0.6.1-1mamba +- package created by silvan using the webbuild interface