103 lines
3.6 KiB
Diff
103 lines
3.6 KiB
Diff
From c72af29f0bd82678918b941654aff892fbd7dc8a Mon Sep 17 00:00:00 2001
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From: Aleksei Nurmukhametov <aleksei.nurmukhametov@intel.com>
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Date: Thu, 29 Feb 2024 08:59:44 -0800
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Subject: [PATCH] llvm_patches: add x86-isel fix
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This backported patch fixes generation of redundant vmovd, vpinsrd
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instructions.
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Test case added as XFAIL until LLVM rebuild in CI.
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---
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...auxShuffleMask-handle-fp-int-bitcast.patch | 40 +++++++++++++++++++
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tests/lit-tests/2777.ispc | 34 ++++++++++++++++
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2 files changed, 74 insertions(+)
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create mode 100644 llvm_patches/16_0_17_0-X86-getFauxShuffleMask-handle-fp-int-bitcast.patch
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create mode 100644 tests/lit-tests/2777.ispc
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diff --git a/llvm_patches/16_0_17_0-X86-getFauxShuffleMask-handle-fp-int-bitcast.patch b/llvm_patches/16_0_17_0-X86-getFauxShuffleMask-handle-fp-int-bitcast.patch
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new file mode 100644
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index 0000000000..f197b35051
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--- /dev/null
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+++ b/llvm_patches/16_0_17_0-X86-getFauxShuffleMask-handle-fp-int-bitcast.patch
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@@ -0,0 +1,40 @@
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+# This patch is required to fix the issue #2777
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+From 7aa6ddfea210b6b114ac649c4d3219138e9cc52a Mon Sep 17 00:00:00 2001
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+From: Simon Pilgrim <llvm-dev@redking.me.uk>
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+Date: Thu, 29 Feb 2024 10:32:37 +0000
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+Subject: [PATCH] [X86] getFauxShuffleMask - handle
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+ insert_vector_elt(bitcast(extract_vector_elt(x))) shuffle patterns
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+
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+If the bitcast is between types of equal scalar size (i.e. fp<->int bitcasts), then we can safely peek through them
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+
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+Fixes #83289
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+---
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+ llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++++--
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+ 1 file changed, 5 insertions(+), 2 deletions(-)
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+
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+diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
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+index e43b33eed470..22eea8b3d43d 100644
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+--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
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++++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
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+@@ -8477,13 +8477,16 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
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+ }
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+ }
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+
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+- // Peek through trunc/aext/zext.
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++ // Peek through trunc/aext/zext/bitcast.
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+ // TODO: aext shouldn't require SM_SentinelZero padding.
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+ // TODO: handle shift of scalars.
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+ unsigned MinBitsPerElt = Scl.getScalarValueSizeInBits();
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+ while (Scl.getOpcode() == ISD::TRUNCATE ||
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+ Scl.getOpcode() == ISD::ANY_EXTEND ||
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+- Scl.getOpcode() == ISD::ZERO_EXTEND) {
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++ Scl.getOpcode() == ISD::ZERO_EXTEND ||
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++ (Scl.getOpcode() == ISD::BITCAST &&
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++ Scl.getScalarValueSizeInBits() ==
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++ Scl.getOperand(0).getScalarValueSizeInBits())) {
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+ Scl = Scl.getOperand(0);
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+ MinBitsPerElt =
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+ std::min<unsigned>(MinBitsPerElt, Scl.getScalarValueSizeInBits());
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+--
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+2.25.1
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+
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diff --git a/tests/lit-tests/2777.ispc b/tests/lit-tests/2777.ispc
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new file mode 100644
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index 0000000000..ec7656629a
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--- /dev/null
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+++ b/tests/lit-tests/2777.ispc
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@@ -0,0 +1,34 @@
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+// RUN: %{ispc} %s --target=avx2-i32x8 --emit-asm -o - | FileCheck %s
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+
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+// REQUIRES: X86_ENABLED && LLVM_16_0+
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+
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+// XFAIL: *
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+
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+// CHECK-NOT: vmovd
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+// CHECK-NOT: vpinsrd
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+
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+struct FVector4f
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+{
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+ float V[4];
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+};
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+
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+// Extra vmovd, vpinsrd after 2x vmaxps
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+inline uniform FVector4f VectorMax(const uniform FVector4f& V1, const uniform FVector4f& V2)
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+{
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+ varying float S0, S1, Result;
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+ *((uniform FVector4f *uniform)&S0) = *((uniform FVector4f *uniform)&V1);
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+ *((uniform FVector4f *uniform)&S1) = *((uniform FVector4f *uniform)&V2);
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+
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+ Result = max(S0, S1);
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+
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+ return *((uniform FVector4f *uniform)&Result);
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+}
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+
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+export void foo(uniform float A[], uniform float B[])
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+{
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+
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+ uniform FVector4f *uniform pA = (uniform FVector4f *uniform)A;
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+ uniform FVector4f *uniform pB = (uniform FVector4f *uniform)B;
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+
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+ *pA = VectorMax(*pA, *pB);
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+}
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